Semiconductor Device and Method for Evaluating Semiconductor Device

ABSTRACT

A semiconductor layer with a low density of trap states is provided. A transistor with stable electrical characteristics is provided. A transistor having high field-effect mobility is provided. A semiconductor device including the transistor is provided. A method for evaluating a semiconductor layer is provided. A method for evaluating a transistor is provided. A method for evaluating a semiconductor device is provided. Provided is, for example, a semiconductor layer with a low defect density which can be used for a channel formation region of a transistor, a transistor including a semiconductor layer with a low defect density in a channel formation region, or a semiconductor device including the transistor.

This application is a divisional of copending U.S. application Ser. No.14/091,907, filed on Nov. 27, 2013 which is incorporated herein byreference.

BACKGROUND OF THE INVENTION

1. Field of the Invention

The present invention relates to an object, a method, a manufacturingmethod, a process, a machine, manufacture, or a composition of matter.In particular, the present invention relates to, for example, asemiconductor device, a display device, a liquid crystal display device,a light-emitting device, a driving method thereof, or a manufacturingmethod thereof. In particular, the present invention relates to, forexample, a semiconductor device including a transistor, a display deviceincluding a transistor, a liquid crystal display device including atransistor, or a light-emitting device including a transistor, or adriving method thereof. Alternatively, the present invention relates to,for example, an electronic appliance including the semiconductor device,the display device, the liquid crystal display device, or thelight-emitting device.

Note that in this specification, a semiconductor device refers to anydevice that can function by utilizing semiconductor characteristics, andan electro-optical device, a semiconductor circuit, an electronicappliance, and the like are all semiconductor devices.

2. Description of the Related Art

A technique for forming a transistor by using a semiconductor filmformed over a substrate having an insulating surface has attractedattention. The transistor has been widely used for semiconductor devicessuch as integrated circuits and display devices. A silicon film is knownas a semiconductor film applicable to a transistor.

As the silicon film used as a semiconductor film of a transistor, eitheran amorphous silicon film or a polycrystalline silicon film is useddepending on the purpose. For example, in the case of a transistorincluded in a large display device, an amorphous silicon film, which canbe formed using an established technique for forming a film over a largesubstrate, is preferably used. On the other hand, in the case of atransistor included in a high-performance display device where drivercircuits are formed over the same substrate, a polycrystalline siliconfilm, which can form a transistor having high field-effect mobility, ispreferably used. As a method for forming a polycrystalline silicon film,high-temperature heat treatment or laser light treatment which isperformed on an amorphous silicon film has been known.

In recent years, an oxide semiconductor film has attracted attention.For example, a transistor which includes an amorphous oxidesemiconductor film containing indium, gallium, and zinc and having acarrier density lower than 10¹⁸/cm³ is disclosed (see Patent Document1).

An oxide semiconductor film can be formed by a sputtering method or thelike, and thus can be used for a channel formation region of atransistor in a large display device. A transistor including an oxidesemiconductor film has high field-effect mobility; therefore, ahigh-performance display device where driver circuits are formed overthe same substrate can be obtained. Moreover, there is an advantage thatcapital investment can be reduced because part of production equipmentfor a transistor including an amorphous silicon film can be retrofittedand utilized.

REFERENCE Patent Document

-   [Patent Document 1] Japanese Published Patent Application No.    2006-165528

SUMMARY OF THE INVENTION

An object is to provide a semiconductor layer with a low density of trapstates. Another object is to provide a transistor with stable electricalcharacteristics. Another object is to provide a transistor having highfield-effect mobility. Another object is to provide a semiconductordevice including the transistor.

An object is to provide a method for evaluating a semiconductor layer.Another object is to provide a method for evaluating a transistor.Another object is to provide a method for evaluating a semiconductordevice.

Note that the descriptions of these objects do not disturb the existenceof other objects. Note that in one embodiment of the present invention,there is no need to achieve all the objects. Other objects will beapparent from and can be derived from the description of thespecification, the drawings, the claims, and the like.

One embodiment of the present invention is, for example, a semiconductorlayer with a low defect density which can be used for a channelformation region of a transistor, a transistor including a semiconductorlayer with a low defect density in a channel formation region, or asemiconductor device including the transistor.

A channel formation region is or includes, for example, a region whichserves as a main current path when a voltage higher than or equal to thethreshold voltage of a transistor is applied to a gate of thetransistor.

A semiconductor layer with a low defect density is, for example, asemiconductor layer with a low density of trap states or a semiconductorlayer with a low carrier density.

When a transistor includes a semiconductor layer with a high density oftrap states in a channel formation region, for example, charges capturedby the trap states cause fluctuations of electrical characteristics ofthe transistor. Thus, a transistor including a semiconductor layer witha high density of trap states in a channel formation region tends tohave low reliability. Accordingly, it is possible to fabricate atransistor having stable electrical characteristics by using asemiconductor layer with a low density of trap states for a channelformation region of the transistor. Note that examples of fluctuationsof electrical characteristics of a transistor include fluctuations ofthreshold voltage (Vth), an increase in subthreshold swing value (Svalue), a decrease in on-state current (Ion), and an increase inoff-state current (Ioff).

Fluctuations of electrical characteristics of a transistor often causemalfunction of a semiconductor device. Accordingly, it is possible toprovide a highly reliable semiconductor device by using a transistorwith stable electrical characteristics.

Evaluation of defect density in a semiconductor layer becomes moredifficult as the defect density is decreased in most cases. In addition,there are few methods for measuring defects themselves in asemiconductor layer. One example of such methods is to measure theconcentration of impurities that form defects in a semiconductor layerand evaluate the defect density in the semiconductor layer by theconcentration of the impurities. However, with this method, accurateevaluation is possible only when all (or almost all) the impurities inthe semiconductor layer form defects; thus, the measurement target islimited.

In view of this problem, one embodiment of the present invention is, forexample, a method for evaluating defect density in a semiconductorlayer, a method for evaluating defect density in a channel formationregion of a transistor, a method for evaluating reliability of atransistor, or a method for evaluating reliability of a semiconductordevice.

One embodiment of the present invention is, for example, a semiconductordevice including an oxide semiconductor layer, a first electrode, and asecond electrode. The oxide semiconductor layer includes a channelformation region of a transistor and is electrically connected to thefirst electrode and the second electrode. While a voltage is appliedbetween the first electrode and the second electrode, the oxidesemiconductor layer begins to be irradiated with light having a peak ina wavelength range of 340 nm to 360 nm and an intensity of 3 mW/cm² at atemperature of 25° C. at a time T0 and the irradiation is stopped at atime T1. A value of a current flowing between the first electrode andthe second electrode at a time T2 is greater than or equal to 70% andless than 100% of a maximum value of a current flowing between the firstelectrode and the second electrode between the time T0 and the time T1.The time T2 is after a period of greater than or equal to 1 second andless than or equal to 15 seconds from the time T0 and before the timeT1. A value of a current flowing between the first electrode and thesecond electrode at a time T3 is greater than or equal to 5% and lessthan 100% of the maximum value of the current flowing between the firstelectrode and the second electrode between the time T0 and the time T1.The time T3 is after a period of greater than or equal to 1 second andless than or equal to 15 seconds from the time T1.

The semiconductor device of one embodiment of the present inventionincludes, for example, an oxide layer that is in contact with the oxidesemiconductor layer and has a lower electron affinity than an electronaffinity of the oxide semiconductor layer.

The semiconductor device of one embodiment of the present inventionincludes, for example, an insulating film in contact with the oxidesemiconductor layer and a third electrode overlapping with the oxidesemiconductor layer with the insulating film positioned therebetween.

In the semiconductor device of one embodiment of the present invention,for example, the oxide semiconductor layer contains at least indium.

Another embodiment of the present invention is a method for evaluating asemiconductor device including an oxide semiconductor layer, a firstelectrode, and a second electrode. The oxide semiconductor layerincludes a channel formation region of a transistor and is electricallyconnected to the first electrode and the second electrode. The methodincludes the steps of: beginning to irradiate the oxide semiconductorlayer with light having an energy higher than an energy gap of the oxidesemiconductor layer at a time T0 and stopping the irradiation at a timeT1 while a voltage is applied between the first electrode and the secondelectrode; and evaluating a defect in the oxide semiconductor layer bycomparing a value of a current flowing between the first electrode andthe second electrode at a time T2 with a maximum value of a currentflowing between the first electrode and the second electrode between thetime T0 and the time T1 and comparing a value of a current flowingbetween the first electrode and the second electrode at a time T3 withthe maximum value of the current flowing between the first electrode andthe second electrode between the time T0 and the time T1. The time T2 isafter a period of greater than or equal to 1 second and less than orequal to 15 seconds from the time T0 and before the time T1. The time T3is after a period of greater than or equal to 1 second and less than orequal to 15 seconds from the time T1.

For example, the time T2 is five seconds after the time T0, and the timeT3 is five seconds after the time T1.

For example, the time T1 is after a period of greater than or equal to100 seconds and less than or equal to 300 seconds from the time T0.

Note that the above-described embodiments of the present invention areexamples. For example, the semiconductor layer is not limited to theoxide semiconductor layer. For example, a silicon layer, an organicsemiconductor layer, and other compound semiconductor layers (such as agallium arsenide layer, a silicon carbide layer, and a gallium nitridelayer) may be used instead of the oxide semiconductor layer.

According to one embodiment of the present invention, a semiconductorlayer with a low density of trap states can be provided. Further, atransistor with stable electrical characteristics can be provided.Further, a transistor having high field-effect mobility can be provided.In addition, a semiconductor device including the transistor can beprovided.

According to one embodiment of the present invention, a method forevaluating a semiconductor layer can be provided. Further, a method forevaluating a transistor can be provided. Further, a method forevaluating a semiconductor device can be provided.

BRIEF DESCRIPTION OF THE DRAWINGS

FIGS. 1A and 1B are a top view and a cross-sectional view of a sample ofone embodiment of the present invention, and FIG. 1C shows a bandstructure of the sample.

FIGS. 2A1, 2B1, 2C1, and 2D1 show band structures of a sample of oneembodiment of the present invention and FIGS. 2A2, 2B2, 2C2, and 2D2show photoresponse of the sample.

FIGS. 3A and 3B are a top view and a cross-sectional view of a sample ofone embodiment of the present invention, and FIG. 3C shows a bandstructure of the sample.

FIGS. 4A1, 4B1, 4C1, and 4D1 show band structures of a sample of oneembodiment of the present invention and FIGS. 4A2, 4B2, 4C2, and 4D2show photoresponse of the sample.

FIGS. 5A and 5B are a top view and a cross-sectional view of a sample ofone embodiment of the present invention, and FIG. 5C shows a bandstructure of the sample.

FIGS. 6A1, 6B1, 6C1, and 6D1 show band structures of a sample of oneembodiment of the present invention and FIGS. 6A2, 6B2, 6C2, and 6D2show photoresponse of the sample.

FIGS. 7A to 7D are a top view and cross-sectional views illustrating asemiconductor device of one embodiment of the present invention.

FIGS. 8A to 8C are cross-sectional views illustrating a method formanufacturing a semiconductor device of one embodiment of the presentinvention.

FIGS. 9A and 9B are cross-sectional views illustrating a method formanufacturing a semiconductor device of one embodiment of the presentinvention.

FIGS. 10A to 10C are a top view and cross-sectional views illustrating asemiconductor device of one embodiment of the present invention.

FIGS. 11A to 11C are cross-sectional views illustrating a method formanufacturing a semiconductor device of one embodiment of the presentinvention.

FIGS. 12A and 12B are cross-sectional views illustrating a method formanufacturing a semiconductor device of one embodiment of the presentinvention.

FIG. 13 is a circuit diagram illustrating an example of an EL displaydevice of one embodiment of the present invention.

FIGS. 14A to 14C are a top view and cross-sectional views illustratingan example of an EL display device of one embodiment of the presentinvention.

FIGS. 15A and 15B are cross-sectional views illustrating examples of ELdisplay devices of one embodiment of the present invention.

FIG. 16 is a circuit diagram illustrating an example of a liquid crystaldisplay device of one embodiment of the present invention.

FIGS. 17A to 17C are cross-sectional views illustrating examples ofliquid crystal display devices of one embodiment of the presentinvention.

FIGS. 18A1, 18A2, 18B1, 18B2, 18C1, and 18C2 are cross-sectional viewseach illustrating an example of a pixel of a liquid crystal displaydevice of one embodiment of the present invention.

FIGS. 19A1, 19A2, 19B1, and 19B2 are cross-sectional views eachillustrating an example of a pixel of a liquid crystal display device ofone embodiment of the present invention.

FIGS. 20A1, 20A2, 20B1, and 20B2 are cross-sectional views eachillustrating an example of a pixel of a liquid crystal display device ofone embodiment of the present invention.

FIGS. 21A and 21B are a top view and a cross-sectional view illustratingan example of a pixel of a liquid crystal display device of oneembodiment of the present invention.

FIGS. 22A to 22C are top views each illustrating an example of a pixelof a liquid crystal display device of one embodiment of the presentinvention.

FIGS. 23A to 23C are top views each illustrating an example of a pixelof a liquid crystal display device of one embodiment of the presentinvention.

FIGS. 24A to 24C are views for explaining a touch sensor of anembodiment.

FIGS. 25A and 25B illustrate a pixel provided with a touch sensor of anembodiment.

FIGS. 26A and 26B illustrate operations of touch sensors and pixels ofan embodiment.

FIG. 27 is a timing chart showing operations of touch sensors and pixelsof an embodiment.

FIGS. 28A to 28C each illustrate a structure of a pixel of anembodiment.

FIG. 29 is a block diagram illustrating an example of a semiconductordevice of one embodiment of the present invention.

FIG. 30 is a cross-sectional view illustrating an example of asemiconductor device of one embodiment of the present invention.

FIGS. 31A to 31C are block diagrams illustrating examples of CPUs of oneembodiment of the present invention.

FIGS. 32A to 32C illustrate examples of electronic appliances of oneembodiment of the present invention.

FIGS. 33A and 33B are a top view and a cross-sectional view of a sampleof one embodiment of the present invention.

FIG. 34 shows spectra of irradiation light.

FIGS. 35A to 35D show photoresponse of samples.

FIGS. 36A to 36D show photoresponse of samples.

FIGS. 37A to 37D illustrate cross-sectional structures of transistors.

FIG. 38 shows a spectrum of irradiation light.

FIGS. 39A and 39B show ΔVth and ΔShift of transistors between before andafter GBT tests.

FIGS. 40A and 40B show photoresponse of samples.

FIGS. 41A and 41B show photoresponse of samples.

FIGS. 42A and 42B show photoresponse of samples.

FIGS. 43A and 43B show photoresponse of samples.

FIGS. 44A and 44B show photoresponse of samples.

FIGS. 45A and 45B show photoresponse of samples.

DETAILED DESCRIPTION OF THE INVENTION

Embodiments will be hereinafter described with reference to theaccompanying drawings. Note that the embodiments can be implemented withvarious modes, and it will be readily appreciated by those skilled inthe art that modes and details can be changed in various ways withoutdeparting from the spirit and scope of the present invention. Therefore,the present invention is not construed as being limited to descriptionof the embodiments. Note that in structures of the invention describedbelow, the same portions or portions having similar functions aredenoted by common reference numerals, and the descriptions thereof arenot repeated.

Note that what is described (or part thereof) in one embodiment can beapplied to, combined with, or exchanged with another content in the sameembodiment and/or what is described (or part thereof) in anotherembodiment or other embodiments.

Note that in each embodiment, a content described in the embodiment is acontent described with reference to a variety of diagrams or a contentdescribed with texts described in this specification.

In addition, by combining a diagram (or part thereof) described in oneembodiment with another part of the diagram, a different diagram (orpart thereof) described in the same embodiment, and/or a diagram (orpart thereof) described in one or a plurality of different embodiments,much more diagrams can be formed.

Embodiments of the present invention will be described in detail withreference to the accompanying drawings. Note that the present inventionis not limited to the description below, and it is easily understood bythose skilled in the art that modes and details disclosed herein can bemodified in various ways. Therefore, the present invention is notconstrued as being limited to description of the embodiments. Indescribing structures of the present invention with reference to thedrawings, the same reference numerals are used in common for the sameportions in different drawings. The same hatching pattern is applied tosimilar parts, and the similar parts are not especially denoted byreference numerals in some cases.

Note that the size, the thickness of a layer, or a region in diagrams issometimes exaggerated for simplicity. Therefore, embodiments of thepresent invention are not limited to such scales.

Note that diagrams are schematic views of ideal examples, and shapes orvalues are not limited to those illustrated in the diagrams. Forexample, the following can be included: variation in shape due to amanufacturing technique or dimensional deviation; or variation insignal, voltage, or current due to noise or difference in timing.

Note that a voltage refers to a potential difference between a certainpotential and a reference potential (e.g., a ground potential (GND) or asource potential) in many cases. Accordingly, a voltage can also becalled a potential.

Further, even when the expression “to be electrically connected” is usedin this specification, there is a case in which no physical connectionis made and a wiring is just extended in an actual circuit.

Note that technical terms are used in order to describe a specificembodiment, example, or the like in many cases. One embodiment of thepresent invention should not be construed as being limited by thetechnical terms.

Terms which are not defined in this specification (including terms usedfor science and technology, such as technical terms or academic terms)can be used as the terms having meaning equal to general meaning that anordinary person skilled in the art understands. It is preferable thatterms defined by dictionaries or the like be construed to have meaningsconsistent with the background of related art.

Note that the ordinal numbers such as “first” and “second” in thisspecification are used for convenience and do not denote the order ofsteps or the stacking order of layers. In addition, the ordinal numbersin this specification do not denote particular names which specify thepresent invention.

Note that a content which is not specified in any drawing or text in thespecification can be excluded from the invention. When the number rangeof values indicated by e.g., the maximum value and the minimum value isdescribed, the range may be freely narrowed or a value in the range maybe excluded, so that the invention can be specified by a range resultingfrom exclusion of part of the range. In this manner, it is possible tospecify the technical scope of the present invention so that aconventional technology is excluded, for example.

Specifically, for example, a diagram of a circuit including first tofifth transistors is described. In that case, it can be specified thatthe circuit does not include a sixth transistor in the invention. It canbe specified that the circuit does not include a capacitor in theinvention. It can be specified that the circuit does not include a sixthtransistor with a particular connection structure in the invention. Itcan be specified that the circuit does not include a capacitor with aparticular connection structure in the invention. For example, it can bespecified that a sixth transistor whose gate is connected to a gate ofthe third transistor is not included in the invention. For example, itcan be specified that a capacitor whose first electrode is connected tothe gate of the third transistor is not included in the invention.

As another specific example, a description of a value, “a voltage ispreferably higher than or equal to 3 V and lower than or equal to 10 V”is given. In that case, for example, it can be specified that the casewhere the voltage is higher than or equal to −2 V and lower than orequal to 1 V is excluded from the invention. For example, it can bespecified that the case where the voltage is higher than or equal to 13V is excluded from the invention. Note that, for example, it can bespecified that the voltage is higher than or equal to 5 V and lower thanor equal to 8 V in the invention. Note that, for example, it can bespecified that the voltage is approximately 9 V in the invention. Notethat, for example, it can be specified that the voltage is higher thanor equal to 3 V and lower than or equal to 10 V but is not 9 V in theinvention.

As another specific example, a description of a value, “a voltage ispreferably 10 V” is given. In that case, for example, it can bespecified that the case where the voltage is higher than or equal to −2V and lower than or equal to 1 V is excluded from the invention. Forexample, it can be specified that the case where the voltage is higherthan or equal to 13 V is excluded from the invention.

As another specific example, a description of a property of a material,“a film is an insulating film”, is given. In that case, for example, itcan be specified that the case where the insulating film is an organicinsulating film is excluded from the invention. For example, it can bespecified that the case where the insulating film is an inorganicinsulating film is excluded from the invention.

As another specific example, a description of a stacked structure, “afilm is provided between A and B” is given. In that case, for example,it can be specified that the case where the film is a stacked film offour or more layers is excluded from the invention. For example, it canbe specified that the case where a conductive film is provided between Aand the film is excluded from the invention.

<1. Oxide Semiconductor Layer>

A structure of an oxide semiconductor layer which can be used for achannel formation region of a transistor will be described below. Inparticular, an oxide semiconductor layer with a low density of trapstates will be described. Also described is a method for evaluating trapstates in the oxide semiconductor layer on the basis of a change in theconductivity of the oxide semiconductor layer that is caused by light(also referred to as photoresponse).

An oxide semiconductor layer is described below. Note that oneembodiment of the present invention is not limited to the oxidesemiconductor layer. For example, a silicon layer, an organicsemiconductor layer, and other compound semiconductor layers (such as agallium arsenide layer, a silicon carbide layer, and a gallium nitridelayer) may be used instead of the oxide semiconductor layer.

An oxide semiconductor layer used for a channel formation region of atransistor is preferably, for example, an oxide semiconductor layer witha low defect density. For example, a defect in an oxide semiconductorlayer may be formed by plasma that is used for etching by a dry etchingmethod or the like or plasma that is used for deposition by a chemicalvapor deposition (CVD) method or the like. Alternatively, a defect in anoxide semiconductor may be formed by collision of sputtered particlesduring deposition by a sputtering method, for example.

An oxide semiconductor layer with a low defect density is, for example,an oxide semiconductor layer with a low density of trap states or anoxide semiconductor layer with a low carrier density. Examples of adefect in an oxide semiconductor layer include a defect due to an oxygenvacancy and a defect caused by entry of an impurity element (e.g.,hydrogen or silicon). It is often difficult to identify which defect inthe oxide semiconductor layer serves as a trap state, a donor, or anacceptor. In any case, defects can cause fluctuations of electricalcharacteristics of a transistor; therefore, it is important to removefactors of defect formation as much as possible.

For example, when a transistor includes an oxide semiconductor layerwith a high density of trap states in a channel formation region,charges captured by the trap states cause fluctuations of electricalcharacteristics of the transistor in some cases. Thus, a transistorincluding an oxide semiconductor layer with a high density of trapstates in a channel formation region tends to have low reliability.Accordingly, it is preferable to use an oxide semiconductor layer with alow density of trap states for a channel formation region of atransistor.

<1-1. Evaluation of Trap States in Oxide Semiconductor Layer>

The effect on photoresponse of the density of trap states in an oxidesemiconductor layer will be described.

<1-1-1. Model A>

Model A is described with reference to FIGS. 1A to 1C. FIG. 1A is a topview of a sample which serves as Model A (hereinafter called Sample A).Note that an insulating film 112, an insulating film 118, and the likeare not illustrated in FIG. 1A for easy understanding.

FIG. 1B is a cross-sectional view of Sample A taken along dashed-dottedline A1-B1 in FIG. 1A.

FIG. 1B is a cross-sectional view of Sample A including a substrate 100;the insulating film 112 provided over the substrate 100; a multilayerfilm 106 a including an oxide semiconductor layer 106 a 1 provided overthe insulating film 112 and an oxide semiconductor layer 106 a 2provided over the oxide semiconductor layer 106 a 1; an electrode 116 aand an electrode 116 b provided over and in contact with the multilayerfilm 106 a; and the insulating film 118 provided over the multilayerfilm 106 a, the electrode 116 a, and the electrode 116 b.

FIG. 1C shows a band structure which corresponds to a cross section ofSample A taken along dashed-dotted line X1-Y1 in FIG. 1B. Note that thedotted lines in the oxide semiconductor layer 106 a 1 and the oxidesemiconductor layer 106 a 2 in FIG. 1C indicate trap states.

The oxide semiconductor layer 106 a 1 in Sample A is an oxidesemiconductor layer having higher electron affinity than that of theoxide semiconductor layer 106 a 2. For example, as the oxidesemiconductor layer 106 a 1, an oxide semiconductor layer having higherelectron affinity than that of the oxide semiconductor layer 106 a 2 bygreater than or equal to 0.07 eV and less than or equal to 1.3 eV,preferably greater than or equal to 0.1 eV and less than or equal to 0.7eV, more preferably greater than or equal to 0.15 eV and less than orequal to 0.4 eV is used. Note that the electron affinity refers to anenergy gap between the vacuum level and the bottom of the conductionband.

As each of the oxide semiconductor layer 106 a 1 and the oxidesemiconductor layer 106 a 2, an oxide semiconductor layer having a largeenergy gap is used. For example, the energy gap of the oxidesemiconductor layer 106 a 1 is greater than or equal to 2.5 eV and lessthan or equal to 4.2 eV, preferably greater than or equal to 2.8 eV andless than or equal to 3.8 eV, more preferably greater than or equal to 3eV and less than or equal to 3.5 eV. Further, for example, the energygap of the oxide semiconductor layer 106 a 2 is greater than or equal to2.7 eV and less than or equal to 4.9 eV, preferably greater than orequal to 3 eV and less than or equal to 4.7 eV, more preferably greaterthan or equal to 3.2 eV and less than or equal to 4.4 eV. Note that asthe oxide semiconductor layer 106 a 2, an oxide semiconductor layerhaving a larger energy gap than that of the oxide semiconductor layer106 a 1 is used.

An oxide semiconductor layer with a low carrier density is used as eachof the oxide semiconductor layer 106 a 1 and the oxide semiconductorlayer 106 a 2. For example, an oxide semiconductor layer whose carrierdensity is lower than or equal to 1×10¹⁷/cm³, preferably lower than orequal to 1×10¹⁵/cm³, more preferably lower than or equal to 1×10¹³/cm³,still more preferably lower than or equal to 1×10¹¹/cm³ is used as theoxide semiconductor layer 106 a 1. For example, an oxide semiconductorlayer whose carrier density is lower than or equal to 1×10¹⁵/cm³,preferably lower than or equal to 1×10¹³/cm³, more preferably lower thanor equal to 1×10¹¹/cm³, still more preferably lower than or equal to1×10⁹/cm³ is used as the oxide semiconductor layer 106 a 2.

The oxide semiconductor layer 106 a 1 contains at least indium. Inaddition to indium, an element M (aluminum, titanium, silicon, gallium,germanium, yttrium, zirconium, tin, lanthanum, cerium, or hafnium) ispreferably contained.

The oxide semiconductor layer 106 a 2 contains one or more elementsother than oxygen contained in the oxide semiconductor layer 106 a 1.Note that the oxide semiconductor layer 106 a 1 preferably contains atleast indium in order that the carrier mobility (electron mobility) ishigh. Since the oxide semiconductor layer 106 a 2 contains one or moreelements other than oxygen contained in the oxide semiconductor layer106 a 1, interface scattering is unlikely to occur at the interfacebetween the oxide semiconductor layer 106 a 1 and the oxidesemiconductor layer 106 a 2. Thus, the transistor can have highfield-effect mobility because the movement of carriers is not inhibitedat the interface.

The oxide semiconductor layer 106 a 2 may contain, for example,aluminum, titanium, silicon, gallium, germanium, yttrium, zirconium,tin, lanthanum, cerium, or hafnium at a proportion higher than that ofindium. Specifically, the amount of any of the above elements in theoxide semiconductor layer 106 a 2 in an atomic ratio is 1.5 times ormore, preferably 2 times or more, more preferably 3 times or more asmuch as that of indium in an atomic ratio. The above elements increasethe energy gap of the oxide semiconductor layer in some cases. When anyof the above elements is contained in the oxide semiconductor layer at ahigh proportion, it decreases the electron affinity of the oxidesemiconductor layer in some cases. The oxide semiconductor layer 106 a 2contains any of the above elements at a higher proportion than the oxidesemiconductor layer 106 a 1.

In the case of using an In-M-Zn oxide (an element M is aluminum,titanium, silicon, gallium, germanium, yttrium, zirconium, tin,lanthanum, cerium, or hafnium) as the oxide semiconductor layer 106 a 1,the atomic ratio of In to M is preferably as follows: the percentage ofIn is higher than or equal to 25 atomic % and the percentage of M islower than 75 atomic %; further preferably, the percentage of In ishigher than or equal to 34 atomic % and the percentage of M is lowerthan 66 atomic %. In the case of using an In-M-Zn oxide as the oxidesemiconductor layer 106 a 2, the atomic ratio of In to M is preferablyas follows: the percentage of In is lower than 50 atomic % and thepercentage of M is higher than or equal to 50 atomic %; furtherpreferably, the percentage of In is lower than 25 atomic % and thepercentage of M is higher than or equal to 75 atomic %.

The thickness of the oxide semiconductor layer 106 a 2 is greater thanor equal to 3 nm and less than or equal to 100 nm, preferably greaterthan or equal to 3 nm and less than or equal to 50 nm. The thickness ofthe oxide semiconductor layer 106 a 1 is greater than or equal to 3 nmand less than or equal to 200 nm, preferably greater than or equal to 3nm and less than or equal to 100 nm, more preferably greater than orequal to 3 nm and less than or equal to 50 nm.

In Sample A, owing to the formation of the insulating film 118, there isa region where the oxide semiconductor layer 106 a 2 has a higherdensity of trap states than that of the oxide semiconductor layer 106 a1. In other words, there is a region where the oxide semiconductor layer106 a 1 has a lower density of trap states than that of the oxidesemiconductor layer 106 a 2.

Next, description is given with reference to FIGS. 2A1, 2A2, 2B1, 2B2,2C1, 2C2, 2D1, and 2D2 on changes in current value of Sample A in FIGS.1A to 1C in the following case: while voltage is applied between theelectrode 116 a and the electrode 116 b, the multilayer film 106 a isirradiated with light and then light irradiation is stopped. Note thatFIGS. 2A1, 2B1, 2C1, and 2D1 are models corresponding to the bandstructure in FIG. 1C. FIG. 2A2, FIG. 2B2, FIG. 2C2, and FIG. 2D2 showchanges in the value of current flowing between the electrode 116 a andthe electrode 116 b in the models of FIG. 2A1, FIG. 2B1, FIG. 2C1, andFIG. 2D1, respectively. The current value is divided by the maximumcurrent value to be normalized. The energy of the light (denoted by“light” in the drawings) with which the multilayer film 106 a isirradiated is higher than the energy gaps of both the oxidesemiconductor layer 106 a 1 and the oxide semiconductor layer 106 a 2.

First, voltage is applied between the electrode 116 a and the electrode116 b of Sample A without the multilayer film 106 a being irradiatedwith light. In this case, current hardly flows between the electrode 116a and the electrode 116 b because the oxide semiconductor layer 106 a 1and the oxide semiconductor layer 106 a 2 each have a sufficiently lowcarrier density.

Next, upon irradiation of the multilayer film 106 a at a time T0, in theoxide semiconductor layer 106 a 1 and the oxide semiconductor layer 106a 2, electrons (denoted by “electron” in the drawings) in the valenceband are excited to the conduction band and holes (denoted by “hole” inthe drawings) are generated in the valence band; thus, current begins toflow between the electrode 116 a and the electrode 116 b (see FIGS. 2A1and 2A2).

Then, the excited electrons move from the oxide semiconductor layer 106a 2 to the oxide semiconductor layer 106 a 1, so that the electrondensity in the oxide semiconductor layer 106 a 1 is increased. Thegenerated electrons move rapidly because there is no barrier between theoxide semiconductor layer 106 a 2 and the oxide semiconductor layer 106a 1. Here, since the oxide semiconductor layer 106 a 1 includes a regionwith a low density of trap states, movement of electrons is hardlyinhibited; thus, Sample A has high conductivity. Accordingly, a largeamount of current rapidly flows between the electrode 116 a and theelectrode 116 b when the multilayer film 106 a is irradiated with light.Meanwhile, the generated holes are partly captured by the trap states inthe multilayer film 106 a. When recombination of electrons and holes(e.g., band-to-band recombination, band-to-state recombination, orstate-to-state recombination) comes in balance with the generation ofelectrons and holes due to light, the increase in current value stops.Thus, when light irradiation is continued, the value of current flowingbetween the electrode 116 a and the electrode 116 b is brought close toa certain value (see FIGS. 2B1 and 2B2).

Note that in this embodiment, the measurement temperature is roomtemperature; however, the measurement temperature is not limited theretoand may be, for example, a temperature within the range of −40° C. to150° C.

Further, in this embodiment, the energy of the irradiation light ishigher than the energy gaps of both the oxide semiconductor layer 106 a1 and the oxide semiconductor layer 106 a 2; however, the energy of theirradiation light may be lower than the energy gaps of both the oxidesemiconductor layer 106 a 1 and the oxide semiconductor layer 106 a 2.For example, light having a peak in a wavelength range from 440 urn to460 nm or light having a peak in a wavelength range from 540 nm to 560nm may be used for irradiation.

Further, in this embodiment, the irradiation light has an intensity of 3mW/cm²; however, the irradiation light may have a different intensity.For example, light with an intensity within the range of 0.03 mW/cm² to300 mW/cm², preferably an intensity of 0.3 mW/cm² or 30 mW/cm² may beused for irradiation.

Next, light irradiation is stopped at a time T1, so that generation ofelectrons and holes stops. Further, electrons and holes are recombined,so that the number of electrons and holes is reduced. The reduction inthe number of electrons and holes proceeds rapidly in a first step, andproceeds slowly in a second step. In the first step, for example,band-to-band recombination in the oxide semiconductor layer 106 a 1,band-to-state recombination in the oxide semiconductor layer 106 a 1, orstate-to-state recombination in the oxide semiconductor layer 106 a 1and the oxide semiconductor layer 106 a 2 occurs. First, the electrondensity is decreased to some extent in the first step; thus, the amountof current flowing between the electrode 116 a and the electrode 116 bis decreased (see FIGS. 2C1 and 2C2).

Then, the number of electrons and holes is reduced in the second step.In the second step, for example, state-to-state recombination in theoxide semiconductor layer 106 a 2 occurs. Since the oxide semiconductorlayer 106 a 2 includes a region with a high density of trap states,holes are captured by the trap states. Further, in Sample A, the oxidesemiconductor layer 106 a 1 has a high electron density in theconduction band. For recombination of holes at the trap states in theoxide semiconductor layer 106 a 2 and electrons in the oxidesemiconductor layer 106 a 1, the electrons should move from theconduction band in the oxide semiconductor layer 106 a 1 to theconduction band in the oxide semiconductor layer 106 a 2. Since theenergy of the bottom of the conduction band in the oxide semiconductorlayer 106 a 2 is higher than that in the oxide semiconductor layer 106 a1, it takes time for the electrons to move. Accordingly, the second stepproceeds slowly. The electron density is decreased gradually, so thatthe amount of current flowing between the electrode 116 a and theelectrode 116 b is decreased gradually (see FIGS. 2D1 and 2D2).

For example, the multilayer film 106 a begins to be irradiated withlight having an energy higher than the energy gaps of both the oxidesemiconductor layer 106 a 1 and the oxide semiconductor layer 106 a 2(e.g., light having a peak in a wavelength range of 340 nm to 360 nm)and an intensity of 3 mW/cm² at room temperature (about 20° C. to 25°C.) at a time T0 and the irradiation is stopped at a time T1. The valueof current flowing between the electrode 116 a and the electrode 116 bat a time T2 is greater than or equal to 70% and less than 100%,preferably greater than or equal to 80% and less than 100%, furtherpreferably greater than or equal to 90% and less than 100% of themaximum value of current flowing between the electrode 116 a and theelectrode 116 b between the time T0 and the time T1. The time T2 isafter a period of greater than or equal to 1 second and less than orequal to 15 seconds from the time T0 and before the time T1. The valueof current flowing between the electrode 116 a and the electrode 116 bat a time T3 is greater than or equal to 5% and less than 100%,preferably greater than or equal to 10% and less than 100%, furtherpreferably greater than or equal to 15% and less than 100% of themaximum value of the current flowing between the electrode 116 a and theelectrode 116 b between the time T0 and the time T1. The time T3 isafter a period of greater than or equal to 1 second and less than orequal to 15 seconds from the time T1.

As described above, when the multilayer film 106 a is used for atransistor, the oxide semiconductor layer 106 a 1 with a high electronaffinity serves as a channel formation region of the transistor. Sincethe oxide semiconductor layer 106 a 1 includes a region with a lowdensity of trap states, the transistor can have stable electricalcharacteristics.

<1-1-2. Model B>

Model B is described with reference to FIGS. 3A to 3C. FIG. 3A is a topview of a sample which serves as Model B (hereinafter called Sample B).Note that the insulating film 112, the insulating film 118, and the likeare not illustrated in FIG. 3A for easy understanding.

FIG. 3B is a cross-sectional view of Sample B taken along dashed-dottedline A2-B2 in FIG. 3A.

FIG. 3B is a cross-sectional view of Sample B including the substrate100; the insulating film 112 provided over the substrate 100; an oxidesemiconductor layer 106 b provided over the insulating film 112; theelectrode 116 a and the electrode 116 b provided over and in contactwith the oxide semiconductor layer 106 b; and the insulating film 118provided over the oxide semiconductor layer 106 b, the electrode 116 a,and the electrode 116 b.

FIG. 3C shows a band structure which corresponds to a cross section ofSample B taken along dashed-dotted line X2-Y2 in FIG. 3B. Note that thedotted lines in the oxide semiconductor layer 106 b in FIG. 3C indicatetrap states.

An oxide semiconductor layer with a wide energy gap is used as the oxidesemiconductor layer 106 b. For example, the energy gap of the oxidesemiconductor layer 106 b is greater than or equal to 2.5 eV and lessthan or equal to 4.2 eV, preferably greater than or equal to 2.8 eV andless than or equal to 3.8 eV, more preferably greater than or equal to 3eV and less than or equal to 3.5 eV.

An oxide semiconductor layer with a low carrier density is used as theoxide semiconductor layer 106 b. For example, an oxide semiconductorlayer whose carrier density is lower than or equal to 1×10¹⁷/cm³,preferably lower than or equal to 1×10¹⁵/cm³, more preferably lower thanor equal to 1×10¹³/cm³, still more preferably lower than or equal to1×10¹¹/cm³ is used as the oxide semiconductor layer 106 b.

The oxide semiconductor layer 106 b contains at least indium. Inaddition to indium, an element M (aluminum, titanium, silicon, gallium,germanium, yttrium, zirconium, tin, lanthanum, cerium, or hafnium) ispreferably contained.

In the case of using an In-M-Zn oxide (an element M is aluminum,titanium, silicon, gallium, germanium, yttrium, zirconium, tin,lanthanum, cerium, or hafnium) as the oxide semiconductor layer 106 b,the atomic ratio of In to M is preferably as follows: the percentage ofIn is higher than or equal to 25 atomic % and the percentage of M islower than 75 atomic %; further preferably, the percentage of In ishigher than or equal to 34 atomic % and the percentage of M is lowerthan 66 atomic %.

The thickness of the oxide semiconductor layer 106 b is greater than orequal to 3 nm and less than or equal to 200 nm, preferably greater thanor equal to 5 nm and less than or equal to 70 nm, more preferablygreater than or equal to 10 nm and less than or equal to 50 nm.

In Sample B, owing to the formation of the insulating film 118, there isa region with a high density of trap states on the insulating film 118side of the oxide semiconductor layer 106 b. In other words, the oxidesemiconductor layer 106 b includes a region with a low density of trapstates on the insulating film 112 side.

Next, description is given with reference to FIGS. 4A1, 4A2, 4B1, 4B2,4C1, 4C2, 4D1, and 4D2 on changes in current value of Sample B in FIGS.3A to 3C in the following case: while voltage is applied between theelectrode 116 a and the electrode 116 b, the oxide semiconductor layer106 b is irradiated with light and then light irradiation is stopped.Note that FIGS. 4A1, 4B1, 4C1, and 4D1 are models corresponding to theband structure in FIG. 3C. FIG. 4A2, FIG. 4B2, FIG. 4C2, and FIG. 4D2show changes in the value of current flowing between the electrode 116 aand the electrode 116 b in the models of FIG. 4A1, FIG. 4B1, FIG. 4C1,and FIG. 4D1, respectively. The current value is divided by the maximumcurrent value to be normalized. The energy of the light (denoted by“light” in the drawings) with which the oxide semiconductor layer 106 bis irradiated is higher than the energy gap of the oxide semiconductorlayer 106 b.

First, voltage is applied between the electrode 116 a and the electrode116 b of Sample B without the oxide semiconductor layer 106 b beingirradiated with light. In this case, current hardly flows between theelectrode 116 a and the electrode 116 b because the oxide semiconductorlayer 106 b has a sufficiently low carrier density.

Next, upon irradiation of the oxide semiconductor layer 106 b at a timeT0, in the oxide semiconductor layer 106 b, electrons (denoted by“electron” in the drawings) in the valence band are excited to theconduction band and holes (denoted by “hole” in the drawings) aregenerated in the valence band; thus, current begins to flow between theelectrode 116 a and the electrode 116 b. For several milliseconds toseveral tens of milliseconds after irradiation of the oxidesemiconductor layer 106 b, generation of electrons and holes byband-to-band transition mainly occurs (see FIGS. 4A1 and 4A2).

Then, the generated electrons are dispersed in the oxide semiconductorlayer 106 b. Recombination of electrons and holes frequently occurs inthe region with a high density of trap states in the oxide semiconductorlayer 106 b, so that the electron density in the oxide semiconductorlayer 106 b is decreased. Further, since the oxide semiconductor layer106 b has a high density of trap states, movement of electrons is likelyto be inhibited; thus, the conductivity of Sample B is lower than thatof Sample A. Accordingly, the value of current flowing between theelectrode 116 a and the electrode 116 b upon irradiation of the oxidesemiconductor layer 106 b is small. In a period between severalmilliseconds to several tens of milliseconds after irradiation of theoxide semiconductor layer 106 b and several seconds to several minutesafter irradiation of the oxide semiconductor layer 106 b, electronscaptured by trap states are excited to the conduction band, so that theelectron density in the conduction band is increased. This is presumablybecause the excitation of the electrons captured by trap states proceedsmore slowly than band-to-band transition. Thus, upon irradiation of theoxide semiconductor layer 106 b, the current value is graduallyincreased instead of being rapidly increased (see FIGS. 4B 1 and 4B2).

Next, light irradiation is stopped at a time T1, so that generation ofelectrons and holes stops. Further, electrons and holes are recombined,so that the number of electrons and holes is reduced. The reduction inthe number of electrons and holes in Sample B proceeds rapidly. Thereduction in the number of electrons and holes in Sample B is attributedto, for example, band-to-band recombination, band-to-staterecombination, or state-to-state recombination in the oxidesemiconductor layer 106 b. In Sample B, since the oxide semiconductorlayer 106 b includes a region with a high density of trap states, almostall the electrons and holes are recombined by state-to-staterecombination or the like in the region and disappear, so that theamount of current flowing between the electrode 116 a and the electrode116 b is rapidly decreased. Further, electrons captured by trap statesare recombined immediately if they are excited to the conduction band;thus, the electron density in the conduction band becomes extremely low(see FIGS. 4C1 and 4C2).

Next, a small number of electrons and holes that remain are recombinedand disappear, so that the amount of current flowing between theelectrode 116 a and the electrode 116 b is further decreased (see FIGS.4D1 and 4D2).

For example, the oxide semiconductor layer 106 b begins to be irradiatedwith light having an energy higher than the energy gap of the oxidesemiconductor layer 106 b (e.g., light having a peak in a wavelengthrange of 340 nm to 360 nm) and an intensity of 3 mW/cm² at roomtemperature (about 20° C. to 25° C.) at a time T0 and the irradiation isstopped at a time T1. The value of current flowing between the electrode116 a and the electrode 116 b at a time T2 is greater than or equal to30% and less than 100%, preferably greater than or equal to 40% and lessthan 100%, further preferably greater than or equal to 50% and less than100% of the maximum value of current flowing between the electrode 116 aand the electrode 116 b between the time T0 and the time T1. The time T2is after a period of greater than or equal to 1 second and less than orequal to 15 seconds from the time T0 and before the time T1. The valueof current flowing between the electrode 116 a and the electrode 116 bat a time T3 is greater than or equal to 1% and less than 100%,preferably greater than or equal to 2% and less than 100%, furtherpreferably greater than or equal to 5% and less than 100% of the maximumvalue of the current flowing between the electrode 116 a and theelectrode 116 b between the time T0 and the time T1. The time T3 isafter a period of greater than or equal to 1 second and less than orequal to 15 seconds from the time T1.

As described above, when the oxide semiconductor layer 106 b is used fora transistor, the switching characteristics of the transistor are likelyto be degraded because the oxide semiconductor layer 106 b includes aregion with a high density of trap states. Therefore, in the case wherea single oxide semiconductor layer, like the oxide semiconductor layer106 b, is used for a channel formation region of a transistor, treatmentfor decreasing the density of trap states caused owing to the insulatingfilm 118 or the like is preferably performed.

The use of an oxide semiconductor layer with a low density of trapstates makes it possible to provide a transistor with stable electricalcharacteristics.

<1-1-3. Model C>

Model C is described with reference to FIGS. 5A to 5C. FIG. 5A is a topview of a sample which serves as Model C (hereinafter called Sample C).Note that the insulating film 112, the insulating film 118, and the likeare not illustrated in FIG. 5A for easy understanding.

FIG. 5B is a cross-sectional view of Sample C taken along dashed-dottedline A3-B3 in FIG. 5A.

FIG. 5B is a cross-sectional view of Sample C including the substrate100; the insulating film 112 provided over the substrate 100; amultilayer film 106 c including an oxide semiconductor layer 106 c 1provided over the insulating film 112 and an oxide semiconductor layer106 c 2 provided over the oxide semiconductor layer 106 c 1; theelectrode 116 a and the electrode 116 b provided over and in contactwith the multilayer film 106 c; and the insulating film 118 providedover the multilayer film 106 c, the electrode 116 a, and the electrode116 b.

FIG. 5C shows a band structure which corresponds to a cross section ofSample C taken along dashed-dotted line X3-Y3 in FIG. 5B. Note that thedotted lines in the oxide semiconductor layer 106 c 2 and the oxidesemiconductor layer 106 c 1 in FIG. 5C indicate trap states.

The oxide semiconductor layer 106 c 2 in Sample C is an oxidesemiconductor layer having higher electron affinity than that of theoxide semiconductor layer 106 c 1. For example, as the oxidesemiconductor layer 106 c 2, an oxide semiconductor layer having higherelectron affinity than that of the oxide semiconductor layer 106 c 1 bygreater than or equal to 0.07 eV and less than or equal to 1.3 eV,preferably greater than or equal to 0.1 eV and less than or equal to 0.7eV, more preferably greater than or equal to 0.15 eV and less than orequal to 0.4 eV is used. Note that the electron affinity refers to anenergy gap between the vacuum level and the bottom of the conductionband.

As each of the oxide semiconductor layer 106 c 2 and the oxidesemiconductor layer 106 c 1, an oxide semiconductor layer having a largeenergy gap is used. For example, the energy gap of the oxidesemiconductor layer 106 c 2 is greater than or equal to 2.5 eV and lessthan or equal to 4.2 eV, preferably greater than or equal to 2.8 eV andless than or equal to 3.8 eV, more preferably greater than or equal to 3eV and less than or equal to 3.5 eV. Further, for example, the energygap of the oxide semiconductor layer 106 c 1 is greater than or equal to2.7 eV and less than or equal to 4.9 eV, preferably greater than orequal to 3 eV and less than or equal to 4.7 eV, more preferably greaterthan or equal to 3.2 eV and less than or equal to 4.4 eV. Note that asthe oxide semiconductor layer 106 c 1, an oxide semiconductor layerhaving a larger energy gap than that of the oxide semiconductor layer106 c 2 is used.

An oxide semiconductor layer with a low carrier density is used as eachof the oxide semiconductor layer 106 c 2 and the oxide semiconductorlayer 106 c 1. For example, an oxide semiconductor layer whose carrierdensity is lower than or equal to 1×10¹⁷/cm³, preferably lower than orequal to 1×10¹⁵/cm³, more preferably lower than or equal to 1×10¹³/cm³,still more preferably lower than or equal to 1×10¹¹/cm³ is used as theoxide semiconductor layer 106 c 2. For example, an oxide semiconductorlayer whose carrier density is lower than or equal to 1×10¹⁵/cm³,preferably lower than or equal to 1×10¹³/cm³, more preferably lower thanor equal to 1×10¹¹/cm³, still more preferably lower than or equal to1×10⁹/cm³ is used as the oxide semiconductor layer 106 c 1.

The oxide semiconductor layer 106 c 2 contains at least indium. Inaddition to indium, an element M (aluminum, titanium, silicon, gallium,germanium, yttrium, zirconium, tin, lanthanum, cerium, or hafnium) ispreferably contained.

The oxide semiconductor layer 106 c 1 contains one or more elementsother than oxygen contained in the oxide semiconductor layer 106 c 2.Note that the oxide semiconductor layer 106 c 2 preferably contains atleast indium in order that the carrier mobility (electron mobility) ishigh. Since the oxide semiconductor layer 106 c 1 contains one or moreelements other than oxygen contained in the oxide semiconductor layer106 c 2, interface scattering is unlikely to occur at the interfacebetween the oxide semiconductor layer 106 c 2 and the oxidesemiconductor layer 106 c 1. Thus, the transistor can have highfield-effect mobility because the movement of carriers is not inhibitedat the interface.

The oxide semiconductor layer 106 c 1 may contain, for example,aluminum, titanium, silicon, gallium, germanium, yttrium, zirconium,tin, lanthanum, cerium, or hafnium at a proportion higher than that ofindium. Specifically, the amount of any of the above elements in theoxide semiconductor layer 106 c 1 in an atomic ratio is 1.5 times ormore, preferably 2 times or more, more preferably 3 times or more asmuch as that of indium in an atomic ratio. The above elements increasethe energy gap of the oxide semiconductor layer in some cases. When anyof the above elements is contained in the oxide semiconductor layer at ahigh proportion, it decreases the electron affinity of the oxidesemiconductor layer in some cases. The oxide semiconductor layer 106 c 1contains any of the above elements at a higher proportion than the oxidesemiconductor layer 106 c 2.

In the case of using an In-M-Zn oxide (an element M is aluminum,titanium, silicon, gallium, germanium, yttrium, zirconium, tin,lanthanum, cerium, or hafnium) as the oxide semiconductor layer 106 c 2,the atomic ratio of In to M is preferably as follows: the percentage ofIn is higher than or equal to 25 atomic % and the percentage of M islower than 75 atomic %; further preferably, the percentage of In ishigher than or equal to 34 atomic % and the percentage of M is lowerthan 66 atomic %. In the case of using an In-M-Zn oxide as the oxidesemiconductor layer 106 c 1, the atomic ratio of In to M is preferablyas follows: the percentage of In is lower than 50 atomic % and thepercentage of M is higher than or equal to 50 atomic %; furtherpreferably, the percentage of In is lower than 25 atomic % and thepercentage of M is higher than or equal to 75 atomic %.

The thickness of the oxide semiconductor layer 106 c 1 is greater thanor equal to 3 nm and less than or equal to 100 nm, preferably greaterthan or equal to 3 nm and less than or equal to 50 nm. The thickness ofthe oxide semiconductor layer 106 c 2 is greater than or equal to 3 nmand less than or equal to 200 nm, preferably greater than or equal to 3nm and less than or equal to 100 nm, more preferably greater than orequal to 3 nm and less than or equal to 50 nm.

In Sample C, owing to the formation of the insulating film 118, there isa region where the oxide semiconductor layer 106 c 2 has a higherdensity of trap states than that of the oxide semiconductor layer 106 c1. In other words, there is a region where the oxide semiconductor layer106 c 1 has a lower density of trap states than that of the oxidesemiconductor layer 106 c 2.

Next, description is given with reference to FIGS. 6A1, 6A2, 6B1, 6B2,6C1, 6C2, 6D1, and 6D2 on changes in current value of Sample C in FIGS.5A to 5C in the following case: while voltage is applied between theelectrode 116 a and the electrode 116 b, the multilayer film 106 c isirradiated with light and then light irradiation is stopped. Note thatFIGS. 6A1, 6B1, 6C1, and 6D1 are models corresponding to the bandstructure in FIG. 5C. FIG. 6A2, FIG. 6B2, FIG. 6C2, and FIG. 6D2 showchanges in the value of current flowing between the electrode 116 a andthe electrode 116 b in the models of FIG. 6A1, FIG. 6B1, FIG. 6C1, andFIG. 6D1, respectively. The current value is divided by the maximumcurrent value to be normalized. The energy of the light (denoted by“light” in the drawings) with which the multilayer film 106 c isirradiated is higher than the energy gaps of both the oxidesemiconductor layer 106 c 1 and the oxide semiconductor layer 106 c 2.

First, voltage is applied between the electrode 116 a and the electrode116 b of Sample C without the multilayer film 106 c being irradiatedwith light. In this case, current hardly flows between the electrode 116a and the electrode 116 b because the oxide semiconductor layer 106 c 1and the oxide semiconductor layer 106 c 2 each have a sufficiently lowcarrier density.

Next, upon irradiation of the multilayer film 106 c at a time T0, in theoxide semiconductor layer 106 c 1 and the oxide semiconductor layer 106c 2, electrons (denoted by “electron” in the drawings) in the valenceband are excited to the conduction band and holes (denoted by “hole” inthe drawings) are generated in the valence band; thus, current begins toflow between the electrode 116 a and the electrode 116 b (see FIGS. 6A1and 6A2).

Then, the excited electrons move from the oxide semiconductor layer 106c 1 to the oxide semiconductor layer 106 c 2, so that the electrondensity in the oxide semiconductor layer 106 c 2 is increased. Thegenerated electrons move rapidly because there is no barrier between theoxide semiconductor layer 106 c 1 and the oxide semiconductor layer 106c 2. Here, since the oxide semiconductor layer 106 c 2 includes a regionwith a high density of trap states, movement of electrons is likely tobe inhibited. Accordingly, Sample C has a higher conductivity than thatof Sample B, but has a lower conductivity than that of Sample A. Thus,upon irradiation of the multilayer film 106 c, the value of currentflowing between the electrode 116 a and the electrode 116 b istemporarily increased, and then is temporarily decreased becauseelectrons are captured by the trap states in the oxide semiconductorlayer 106 c 2. After that, the trap states are filled with electrons, sothat the current value is increased again. Meanwhile, the generatedholes are partly captured by the trap states in the multilayer film 106c. When recombination of electrons and holes (e.g., band-to-bandrecombination, band-to-state recombination, or state-to-staterecombination) comes in balance with the generation of electrons andholes due to light, the increase in current value stops. Thus, whenlight irradiation is continued, the value of current flowing between theelectrode 116 a and the electrode 116 b is brought close to a certainvalue (see FIGS. 6B1 and 6B2).

Next, light irradiation is stopped at a time T1, so that generation ofelectrons and holes stops. Further, electrons and holes are recombined,so that the number of electrons and holes is reduced. The reduction inthe number of electrons and holes in Sample C proceeds rapidly. Thereduction in the number of electrons and holes in Sample C is attributedto, for example, band-to-band recombination in the oxide semiconductorlayer 106 c 2, band-to-state recombination in the oxide semiconductorlayer 106 c 2, or state-to-state recombination in the oxidesemiconductor layer 106 c 1 and the oxide semiconductor layer 106 c 2.In Sample C, since the oxide semiconductor layer 106 c 2 has a highelectron density in the conduction band and includes a region with ahigh density of trap states, almost all the electrons and holes arerecombined by state-to-state recombination in the oxide semiconductorlayer 106 c 2 and disappear, so that the amount of current flowingbetween the electrode 116 a and the electrode 116 b is rapidly decreased(see FIGS. 6C1 and 6C2).

Next, a small number of electrons and holes that remain are recombinedand disappear, so that the amount of current flowing between theelectrode 116 a and the electrode 116 b is further decreased (see FIGS.6D1 and 6D2).

For example, the multilayer film 106 c begins to be irradiated withlight having an energy higher than the energy gaps of both the oxidesemiconductor layer 106 c 1 and the oxide semiconductor layer 106 c 2(e.g., light having a peak in a wavelength range of 340 nm to 360 nm)and an intensity of 3 mW/cm² at room temperature (about 20° C. to 25°C.) at a time T0 and the irradiation is stopped at a time T1. The valueof current flowing between the electrode 116 a and the electrode 116 bat a time T2 is greater than or equal to 90% and less than 100%,preferably greater than or equal to 95% and less than 100%, furtherpreferably greater than or equal to 98% and less than 100% of themaximum value of current flowing between the electrode 116 a and theelectrode 116 b between the time T0 and the time T1. The time T2 isafter a period of greater than or equal to 1 second and less than orequal to 15 seconds from the time T0 and before the time T1. The valueof current flowing between the electrode 116 a and the electrode 116 bat a time T3 is greater than or equal to 0% and less than 10%,preferably greater than or equal to 0% and less than 5%, furtherpreferably greater than or equal to 0% and less than 2% of the maximumvalue of the current flowing between the electrode 116 a and theelectrode 116 b between the time T0 and the time T1. The time T3 isafter a period of greater than or equal to 1 second and less than orequal to 15 seconds from the time T1.

As described above, when the multilayer film 106 c is used for atransistor, the oxide semiconductor layer 106 c 2 with a high electronaffinity serves as a channel formation region of the transistor. Sincethe oxide semiconductor layer 106 c 2 includes a region with a highdensity of trap states, the switching characteristics of the transistorare likely to be degraded. Note that this transistor can be suitablyused in some cases depending on applications.

<2. Transistor>

A transistor including a multilayer film 306 is described below.

<2-1. Transistor Structure (1)>

Here, a bottom-gate transistor is described. In this section, abottom-gate top-contact (BGTC) transistor which is one kind of abottom-gate transistor is described with reference to FIGS. 7A to 7D.

FIGS. 7A to 7D are a top view and cross-sectional views illustrating aBGTC transistor. FIG. 7A is a top view of the transistor. FIG. 7B is across-sectional view taken along dashed-dotted line C1-C2 in FIG. 7A.FIG. 7C is a cross-sectional view taken along dashed-dotted line C3-C4in FIG. 7A.

The transistor illustrated in FIG. 7B includes a gate electrode 304provided over a substrate 300, a gate insulating film 312 provided overthe gate electrode 304, the multilayer film 306 which includes an oxidesemiconductor layer 306 a provided over the gate insulating film 312 andan oxide semiconductor layer 306 b provided over the oxide semiconductorlayer 306 a, a source electrode 316 a and a drain electrode 316 bprovided over the gate insulating film 312 and the multilayer film 306,and a protective insulating film 318 provided over the multilayer film306, the source electrode 316 a, and the drain electrode 316 b.

Note that a conductive film used for the source electrode 316 a and thedrain electrode 316 b takes oxygen away from part of the oxidesemiconductor layer 306 b or forms a mixed layer depending on the kindof the conductive film used for the source electrode 316 a and the drainelectrode 316 b, which results in formation of a source region 306 c anda drain region 306 d in the oxide semiconductor layer 306 b.

In FIG. 7A, the distance between the source electrode 316 a and thedrain electrode 316 b in a region overlapping with the gate electrode304 is called channel length. Note that in the case where the transistorincludes the source region 306 c and the drain region 306 d, thedistance between the source region 306 c and the drain region 306 d in aregion overlapping with the gate electrode 304 may be called channellength.

Note that a channel formation region refers to a region, which overlapswith the gate electrode 304 and is located between the source electrode316 a and the drain electrode 316 b, in the multilayer film 306 (seeFIG. 7B). Further, a channel region refers to a region through whichcurrent mainly flows in the channel formation region. Here, the channelregion is a portion of the oxide semiconductor layer 306 a in thechannel formation region.

Note that as illustrated in FIG. 7A, the gate electrode 304 is providedsuch that the edge of the multilayer film 306 is located on the innerside than the edge of the gate electrode 304. This can suppressgeneration of carriers in the multilayer film 306 due to light enteringfrom the substrate 300 side. In other words, the gate electrode 304functions as a light-blocking film. Note that the edge of the multilayerfilm 306 may be located on the outer side than the edge of the gateelectrode 304.

<2-1-1. Multilayer Film>

The multilayer film 306 and the oxide semiconductor layer 306 a and theoxide layer 306 b which are included in the multilayer film 306 aredescribed below.

The oxide semiconductor layer 306 a is an oxide semiconductor layerhaving higher electron affinity than that of the oxide semiconductorlayer 306 b. For example, as the oxide semiconductor layer 306 a, anoxide semiconductor layer having higher electron affinity than that ofthe oxide semiconductor layer 306 b by greater than or equal to 0.07 eVand less than or equal to 1.3 eV, preferably greater than or equal to0.1 eV and less than or equal to 0.7 eV, more preferably greater than orequal to 0.15 eV and less than or equal to 0.4 eV is used. In that case,when an electric field is applied to the gate electrode 304, a channelis formed in the oxide semiconductor layer 306 a having higher electronaffinity in the multilayer film 306. That is, forming the oxidesemiconductor layer 306 b between the oxide semiconductor layer 306 aand the protective insulating film 318 enables the channel of thetransistor to be formed in the oxide semiconductor layer 306 a which isapart from the protective insulating film 318. In addition, since theoxide semiconductor layer 306 b contains one or more elements other thanoxygen contained in the oxide semiconductor layer 306 a, interfacescattering is unlikely to occur between the oxide semiconductor layer306 a and the oxide semiconductor layer 306 b. Thus, movement ofcarriers is not inhibited between the oxide semiconductor layer 306 aand the oxide semiconductor layer 306 b, which results in an increase inthe field-effect mobility of the transistor. Moreover, an interfacestate is less likely to be formed between the oxide semiconductor layer306 a and the oxide semiconductor layer 306 b. When an interface stateis formed between the oxide semiconductor layer 306 a and the oxidesemiconductor layer 306 b, a second transistor in which the interfacebetween the oxide semiconductor layer 306 a and the oxide semiconductorlayer 306 b serves as a channel and which has different thresholdvoltage from the transistor is formed and the apparent threshold voltageof the transistor is changed in some cases. Thus, with the oxidesemiconductor layer 306 b, variations of electrical characteristics,such as threshold voltage, between transistors can be reduced.

As each of the oxide semiconductor layer 306 a and the oxidesemiconductor layer 306 b, an oxide semiconductor layer having a largeenergy gap is used. For example, the energy gap of the oxidesemiconductor layer 306 a is greater than or equal to 2.5 eV and lessthan or equal to 4.2 eV, preferably greater than or equal to 2.8 eV andless than or equal to 3.8 eV, more preferably greater than or equal to 3eV and less than or equal to 3.5 eV. Further, for example, the energygap of the oxide semiconductor layer 306 b is greater than or equal to2.7 eV and less than or equal to 4.9 eV, preferably greater than orequal to 3 eV and less than or equal to 4.7 eV, more preferably greaterthan or equal to 3.2 eV and less than or equal to 4.4 eV. Note that asthe oxide semiconductor layer 306 b, an oxide semiconductor layer havinga larger energy gap than that of the oxide semiconductor layer 306 a isused.

An oxide semiconductor layer with a low carrier density is used as eachof the oxide semiconductor layer 306 a and the oxide semiconductor layer306 b. For example, an oxide semiconductor layer whose carrier densityis lower than or equal to 1×10¹⁷/cm³, preferably lower than or equal to1×10¹⁵/cm³, more preferably lower than or equal to 1×10¹³/cm³, stillmore preferably lower than or equal to 1×10¹¹/cm³ is used as the oxidesemiconductor layer 306 a. For example, an oxide semiconductor layerwhose carrier density is lower than or equal to 1×10¹⁵/cm³, preferablylower than or equal to 1×10¹³/cm³, more preferably lower than or equalto 1×10¹¹/cm³, still more preferably lower than or equal to 1×10⁹/cm³ isused as the oxide semiconductor layer 306 b.

The oxide semiconductor layer 306 a contains at least indium. Inaddition to indium, an element M (aluminum, titanium, silicon, gallium,germanium, yttrium, zirconium, tin, lanthanum, cerium, or hafnium) ispreferably contained.

The oxide semiconductor layer 306 b contains one or more elements otherthan oxygen contained in the oxide semiconductor layer 306 a. Note thatthe oxide semiconductor layer 306 a preferably contains at least indiumin order that the carrier mobility (electron mobility) is high. Sincethe oxide semiconductor layer 306 b contains one or more elements otherthan oxygen contained in the oxide semiconductor layer 306 a, interfacescattering is unlikely to occur at the interface between the oxidesemiconductor layer 306 a and the oxide semiconductor layer 306 b. Thus,the transistor can have high field-effect mobility because the movementof carriers is not inhibited at the interface.

The oxide semiconductor layer 306 b may contain, for example, aluminum,titanium, silicon, gallium, germanium, yttrium, zirconium, tin,lanthanum, cerium, or hafnium at a proportion higher than that ofindium. Specifically, the amount of any of the above elements in theoxide semiconductor layer 306 b in an atomic ratio is 1.5 times or more,preferably 2 times or more, more preferably 3 times or more as much asthat of indium in an atomic ratio. The above elements increase theenergy gap of the oxide semiconductor layer in some cases. When any ofthe above elements is contained in the oxide semiconductor layer at ahigh proportion, it decreases the electron affinity of the oxidesemiconductor layer in some cases. The oxide semiconductor layer 306 bcontains any of the above elements at a higher proportion than the oxidesemiconductor layer 306 a.

In the case of using an In-M-Zn oxide (an element M is aluminum,titanium, silicon, gallium, germanium, yttrium, zirconium, tin,lanthanum, cerium, or hafnium) as the oxide semiconductor layer 306 a,the atomic ratio of In to M is preferably as follows: the percentage ofIn is higher than or equal to 25 atomic % and the percentage of M islower than 75 atomic %; further preferably, the percentage of In ishigher than or equal to 34 atomic % and the percentage of M is lowerthan 66 atomic %. In the case of using an In-M-Zn oxide as the oxidesemiconductor layer 306 b, the atomic ratio of In to M is preferably asfollows: the percentage of In is lower than 50 atomic % and thepercentage of M is higher than or equal to 50 atomic %; furtherpreferably, the percentage of In is lower than 25 atomic % and thepercentage of M is higher than or equal to 75 atomic %.

The thickness of the oxide semiconductor layer 306 b is greater than orequal to 3 nm and less than or equal to 100 nm, preferably greater thanor equal to 3 nm and less than or equal to 50 nm. The thickness of theoxide semiconductor layer 306 a is greater than or equal to 3 nm andless than or equal to 200 nm, preferably greater than or equal to 3 nmand less than or equal to 100 nm, more preferably greater than or equalto 3 nm and less than or equal to 50 nm.

As described above, the multilayer film 306 is a multilayer film similarto the multilayer film 106 a described in Model A. That is, the oxidesemiconductor layer 306 a is an oxide semiconductor layer similar to theoxide semiconductor layer 106 a 1. Further, the oxide semiconductorlayer 306 b is an oxide semiconductor layer similar to the oxidesemiconductor layer 106 a 2. Note that the multilayer film 306 may be amultilayer film similar to the multilayer film 106 c described in ModelC. Alternatively, the multilayer film 306 may be replaced with the oxidesemiconductor layer 106 b described in Model B. The multilayer film 306is not limited to a stack of two oxide semiconductor layers. Forexample, the multilayer film 306 may include three or more oxidesemiconductor layers. Specifically, the multilayer film 306 may includean oxide semiconductor layer similar to the oxide semiconductor layer306 b, the oxide semiconductor layer 306 a provided over the oxidesemiconductor layer, and the oxide semiconductor layer 306 b providedover the oxide semiconductor layer 306 a.

The concentration of silicon in each of the oxide semiconductor layer306 a and the oxide semiconductor layer 306 b is described below. Inorder to obtain stable electrical characteristics of a transistor, it iseffective to reduce the concentration of impurities in the oxidesemiconductor layer 306 a so that the oxide semiconductor layer 306 a ishighly purified to be intrinsic. The carrier density of the oxidesemiconductor layer 306 a is set to lower than 1×10¹⁷/cm³, lower than1×10¹⁵/cm³, or lower than 1×10¹³/cm³. In the oxide semiconductor layer306 a, a light element, a semimetal element, a metal element, and thelike (lower than 1 atomic %), other than main components serve asimpurities. For example, hydrogen, nitrogen, carbon, silicon, germanium,titanium, and hafnium serve as impurities in the oxide semiconductorlayer 306 a. Thus, the concentrations of impurities in the gateinsulating film 312 and the oxide semiconductor layer 306 b which areadjacent to the oxide semiconductor layer 306 a are preferably reduced.

For example, when silicon is contained in the oxide semiconductor layer306 a, an impurity state is formed. In particular, when silicon existsbetween the oxide semiconductor layer 306 a and the oxide semiconductorlayer 306 b, the impurity state serves as a trap state. For this reason,the concentration of silicon in a region between the oxide semiconductorlayer 306 a and the oxide semiconductor layer 306 b is set to lower than1×10¹⁹ atoms/cm³, preferably lower than 5×10¹⁸ atoms/cm³, morepreferably lower than 2×10¹⁸ atoms/cm³.

Further, hydrogen and nitrogen in the oxide semiconductor layer 306 aform donor states, which increase carrier density. The concentration ofhydrogen in the oxide semiconductor layer 306 a, which is measured bysecondary ion mass spectrometry (SIMS), is set to lower than or equal to2×10²⁰ atoms/cm³, preferably lower than or equal to 5×10¹⁹ atoms/cm³,more preferably lower than or equal to 1×10¹⁹ atoms/cm³, still morepreferably lower than or equal to 5×10¹⁸ atoms/cm³. The concentration ofnitrogen, which is measured by SIMS, is set to lower than 5×10¹⁹atoms/cm³, preferably lower than or equal to 5×10¹⁸ atoms/cm³, morepreferably lower than or equal to 1×10¹⁸ atoms/cm³, still morepreferably lower than or equal to 5×10¹⁷ atoms/cm³.

It is preferable to reduce the concentrations of hydrogen and nitrogenin the oxide semiconductor layer 306 b in order to reduce theconcentrations of hydrogen and nitrogen in the oxide semiconductor layer306 a. The concentration of hydrogen in the oxide semiconductor layer306 b, which is measured by SIMS, is set to lower than or equal to2×10²⁰ atoms/cm³, preferably lower than or equal to 5×10¹⁹ atoms/cm³,more preferably lower than or equal to 1×10¹⁹ atoms/cm³, still morepreferably lower than or equal to 5×10¹⁸ atoms/cm³. The concentration ofnitrogen, which is measured by SIMS, is set to lower than 5×10¹⁹atoms/cm³, preferably lower than or equal to 5×10¹⁸ atoms/cm³, morepreferably lower than or equal to 1×10¹⁸ atoms/cm³, still morepreferably lower than or equal to 5×10¹⁷ atoms/cm³.

A structure of an oxide semiconductor layer which can be used for theoxide semiconductor layer 306 a and the oxide semiconductor layer 306 bis described below. Note that the trigonal and rhombohedral crystalsystems are included in the hexagonal crystal system.

A structure of an oxide semiconductor layer is described below.

An oxide semiconductor layer is classified roughly into a single-crystaloxide semiconductor layer and a non-single-crystal oxide semiconductorlayer. The non-single-crystal oxide semiconductor layer includes any ofan amorphous oxide semiconductor layer, a microcrystalline oxidesemiconductor layer, a polycrystalline oxide semiconductor layer, ac-axis aligned crystalline oxide semiconductor (CAAC-OS) layer, and thelike.

The amorphous oxide semiconductor layer has disordered atomicarrangement and no crystalline component. A typical example thereof isan oxide semiconductor layer in which no crystal part exists even in amicroscopic region, and the whole of the layer is amorphous.

The microcrystalline oxide semiconductor layer includes a microcrystal(also referred to as nanocrystal) with a size greater than or equal to 1nm and less than 10 nm, for example. Thus, the microcrystalline oxidesemiconductor layer has a higher degree of atomic order than theamorphous oxide semiconductor layer. Hence, the density of defect statesof the microcrystalline oxide semiconductor layer is lower than that ofthe amorphous oxide semiconductor layer.

The CAAC-OS layer is one of oxide semiconductor layers including aplurality of crystal parts, and most of the crystal parts each fitinside a cube whose one side is less than 100 nm. Thus, there is a casewhere a crystal part included in the CAAC-OS layer fits inside a cubewhose one side is less than 10 nm, less than 5 nm, or less than 3 nm.The density of defect states of the CAAC-OS layer is lower than that ofthe microcrystalline oxide semiconductor layer. The CAAC-OS layer isdescribed in detail below.

In a transmission electron microscope (TEM) image of the CAAC-OS layer,a boundary between crystal parts, that is, a grain boundary is notclearly observed. Thus, in the CAAC-OS layer, a reduction in electronmobility due to the grain boundary is less likely to occur.

According to the TEM image of the CAAC-OS layer observed in a directionsubstantially parallel to a sample surface (cross-sectional TEM image),metal atoms are arranged in a layered manner in the crystal parts. Eachmetal atom layer has a morphology reflected by a surface over which theCAAC-OS layer is formed (hereinafter, a surface over which the CAAC-OSlayer is formed is referred to as a formation surface) or a top surfaceof the CAAC-OS layer, and is arranged in parallel to the formationsurface or the top surface of the CAAC-OS layer.

In this specification, a term “parallel” indicates that the angle formedbetween two straight lines is greater than or equal to −10° and lessthan or equal to 10°, and accordingly also includes the case where theangle is greater than or equal to −5° and less than or equal to 5°. Inaddition, a term “perpendicular” indicates that the angle formed betweentwo straight lines is greater than or equal to 80° and less than orequal to 100°, and accordingly includes the case where the angle isgreater than or equal to 85° and less than or equal to 95°.

On the other hand, according to the TEM image of the CAAC-OS layerobserved in a direction substantially perpendicular to the samplesurface (plan TEM image), metal atoms are arranged in a triangular orhexagonal configuration in the crystal parts. However, there is noregularity of arrangement of metal atoms between different crystalparts.

From the results of the cross-sectional TEM image and the plan TEMimage, alignment is found in the crystal parts in the CAAC-OS layer.

A CAAC-OS layer is subjected to structural analysis with an X-raydiffraction (XRD) apparatus. For example, when the CAAC-OS layerincluding an InGaZnO₄ crystal is analyzed by an out-of-plane method, apeak appears frequently when the diffraction angle (2θ) is around 31°.This peak is derived from the (009) plane of the InGaZnO₄ crystal, whichindicates that crystals in the CAAC-OS layer have c-axis alignment, andthat the c-axes are aligned in a direction substantially perpendicularto the formation surface or the top surface of the CAAC-OS layer.

On the other hand, when the CAAC-OS layer is analyzed by an in-planemethod in which an X-ray enters a sample in a direction substantiallyperpendicular to the c-axis, a peak appears frequently when 2θ is around56°. This peak is derived from the (110) plane of the InGaZnO₄ crystal.Here, analysis (φ scan) is performed under conditions where the sampleis rotated around a normal vector of a sample surface as an axis (φaxis) with 2θ fixed at around 56°. In the case where the sample is asingle-crystal oxide semiconductor layer of InGaZnO₄, six peaks appear.The six peaks are derived from crystal planes equivalent to the (110)plane. On the other hand, in the case of a CAAC-OS layer, a peak is notclearly observed even when φ scan is performed with 2θ fixed at around56°.

According to the above results, in the CAAC-OS layer having c-axisalignment, while the directions of a-axes and b-axes are differentbetween crystal parts, the c-axes are aligned in a direction parallel toa normal vector of a formation surface or a normal vector of a topsurface. Thus, each metal atom layer arranged in a layered mannerobserved in the cross-sectional TEM image corresponds to a planeparallel to the a-b plane of the crystal.

Note that the crystal part is formed concurrently with deposition of theCAAC-OS layer or is formed through crystallization treatment such asheat treatment. As described above, the c-axis of the crystal is alignedin a direction parallel to a normal vector of a formation surface or anormal vector of a top surface. Thus, for example, in the case where ashape of the CAAC-OS layer is changed by etching or the like, the c-axismight not be necessarily parallel to a normal vector of a formationsurface or a normal vector of a top surface of the CAAC-OS layer.

Further, the degree of crystallinity in the CAAC-OS layer is notnecessarily uniform. For example, in the case where crystal growthleading to the CAAC-OS layer occurs from the vicinity of the top surfaceof the layer, the degree of the crystallinity in the vicinity of the topsurface is higher than that in the vicinity of the formation surface insome cases. Further, when an impurity is added to the CAAC-OS layer, thecrystallinity in a region to which the impurity is added is changed, andthe degree of crystallinity in the CAAC-OS layer varies depending onregions.

Note that when the CAAC-OS layer with an InGaZnO₄ crystal is analyzed byan out-of-plane method, a peak of 2θ may also be observed at around 36°,in addition to the peak of 2θ at around 31°. The peak of 2θ at around36° indicates that a crystal having no c-axis alignment is included inpart of the CAAC-OS layer. It is preferable that in the CAAC-OS layer, apeak of 2θ appear at around 31° and a peak of 2θ do not appear at around36°.

In a transistor using the CAAC-OS layer, change in electricalcharacteristics due to irradiation with visible light or ultravioletlight is small. Thus, the transistor has high reliability.

Note that an oxide semiconductor layer may be a stacked film includingtwo or more layers of an amorphous oxide semiconductor layer, amicrocrystalline oxide semiconductor layer, and a CAAC-OS layer, forexample.

Note that when silicon and carbon are contained in the oxidesemiconductor layer 306 a at a high concentration, the crystallinity ofthe oxide semiconductor layer 306 a is lowered in some cases. In ordernot to lower the crystallinity of the oxide semiconductor layer 306 a,the concentration of silicon in the oxide semiconductor layer 306 a ispreferably set to lower than 1×10¹⁹ atoms/cm³, preferably lower than5×10¹⁸ atoms/cm³, more preferably lower than 2×10¹⁸ atoms/cm³. Moreover,in order not to lower the crystallinity of the oxide semiconductor layer306 a, the concentration of carbon in the oxide semiconductor layer 306a is set to lower than 1×10¹⁹ atoms/cm³, preferably lower than 5×10¹⁸atoms/cm³, more preferably lower than 2×10¹⁸ atoms/cm³.

As described above, in the case where the oxide semiconductor layer 306a in which a channel is formed has high crystallinity and the density ofstates due to an impurity or a defect is low, a transistor including themultilayer film 306 has stable electrical characteristics.

Localized states of the multilayer film 306 are described below. Byreducing the density of localized states due to defect states of themultilayer film 306, a transistor including the multilayer film 306 canhave stable electrical characteristics. The density of localized statesof the multilayer film 306 can be measured by a constant photocurrentmethod (CPM).

In order that the transistor has stable electrical characteristics, theabsorption coefficient due to the localized states of the multilayerfilm 306 measured by CPM is preferably lower than 1×10⁻³ cm⁻¹, morepreferably lower than 3×10⁻⁴ cm⁻¹. Further, when the absorptioncoefficient due to the localized states of the multilayer film 306measured by CPM is lower than 1×10⁻³ cm⁻¹, preferably lower than 3×10⁻⁴cm⁻¹, the field-effect mobility of the transistor can be increased. Inorder that the absorption coefficient due to the localized states of themultilayer film 306 measured by CPM is lower than 1×10⁻³ cm⁻¹,preferably lower than 3×10⁻⁴ cm⁻¹, the concentration of silicon,germanium, carbon, hafnium, titanium, and the like in the oxidesemiconductor layer 306 a which form localized states is preferablylower than 2×10¹⁸ atoms/cm³, more preferably lower than 2×10¹⁷atoms/cm³.

In the CPM measurement, the amount of light with which a surface of thesample between terminals is irradiated is adjusted so that aphotocurrent value is kept constant in the state where voltage isapplied between electrodes provided in contact with the multilayer film306 that is the sample, and then an absorption coefficient is derivedfrom the amount of the irradiation light at each wavelength. In the CPMmeasurement, when the sample has a defect, the absorption coefficient ofenergy which corresponds to a level at which the defect exists(calculated from a wavelength) is increased. The increase in theabsorption coefficient is multiplied by a constant, whereby the defectdensity of the sample can be obtained.

A transistor which includes the multilayer film 306 having a smallabsorption coefficient due to the localized states obtained by CPM hasstable electrical characteristics.

<2-1-2. Source Electrode and Drain Electrode>

The source electrode 316 a and the drain electrode 316 b may be formedusing a single layer or a stacked layer of a conductive film containingone or more kinds of aluminum, titanium, chromium, cobalt, nickel,copper, yttrium, zirconium, molybdenum, ruthenium, silver, tantalum, andtungsten. The source electrode 316 a and the drain electrode 316 b areeach preferably a multilayer film including a layer containing copper.In the case where the source electrode 316 a and the drain electrode 316b are each a multilayer film including a layer containing copper andwhere a wiring is formed in the same layer as the source electrode 316 aand the drain electrode 316 b, wiring resistance can be reduced. Notethat the source electrode 316 a and the drain electrode 316 b may havethe same composition or different compositions.

In the case where a multilayer film including a layer containing copperis used for the source electrode 316 a and the drain electrode 316 b, atrap state might be formed at the interface between the oxidesemiconductor layer 306 b and the protective insulating film 318 due tocopper. Even in this case, since the oxide semiconductor layer 306 aserves as a channel formation region of the transistor owing to theoxide semiconductor layer 306 b, electrons can be prevented from beingcaptured by the trap states. Thus, stable electrical characteristics ofa transistor can be achieved and wiring resistance can be reduced.

<2-1-3. Protective Insulating Film>

The protective insulating film 318 may be formed of a single layer or astacked layer using an insulating film containing one or more kinds ofaluminum oxide, magnesium oxide, silicon oxide, silicon oxynitride,silicon nitride oxide, silicon nitride, gallium oxide, germanium oxide,yttrium oxide, zirconium oxide, lanthanum oxide, neodymium oxide,hafnium oxide, and tantalum oxide.

The protective insulating film 318 may be, for example, a multilayerfilm including a silicon oxide layer as a first layer and a siliconnitride layer as a second layer. In that case, the silicon oxide layermay be a silicon oxynitride layer. In addition, the silicon nitridelayer may be a silicon nitride oxide layer. As the silicon oxide layer,a silicon oxide layer whose defect density is low is preferably used.Specifically, a silicon oxide layer whose spin density attributed to asignal with a g factor of 2.001 in electron spin resonance (ESR) islower than or equal to 3×10¹⁷ spins/cm³, preferably lower than or equalto 5×10¹⁶ spins/cm³ is used. As the silicon nitride layer, a siliconnitride layer from which a hydrogen gas and an ammonia gas are lesslikely to be released is used. The amount of released hydrogen gas orammonia gas may be measured by thermal desorption spectroscopy (TDS).Further, as the silicon nitride layer, a silicon nitride layer whichdoes not transmit or hardly transmits hydrogen, water, and oxygen isused.

Alternatively, the protective insulating film 318 may be, for example, amultilayer film including a first silicon oxide layer 318 a as a firstlayer, a second silicon oxide layer 318 b as a second layer, and asilicon nitride layer 318 c as a third layer (see FIG. 7D). In thatcase, the first silicon oxide layer 318 a and/or the second siliconoxide layer 318 b may be a silicon oxynitride layer. In addition, thesilicon nitride layer may be a silicon nitride oxide layer. As the firstsilicon oxide layer 318 a, a silicon oxide layer whose defect density islow is preferably used. Specifically, a silicon oxide layer whose spindensity attributed to a signal with a g factor of 2.001 in ESR is lowerthan or equal to 3×10¹⁷ spins/cm³, preferably lower than or equal to5×10¹⁶ spins/cm³ is used. As the second silicon oxide layer 318 b, asilicon oxide layer containing excess oxygen is used. As the siliconnitride layer 318 c, a silicon nitride layer from which a hydrogen gasand an ammonia gas are less likely to be released is used. Further, asthe silicon nitride layer, a silicon nitride layer which does nottransmit or hardly transmits hydrogen, water, and oxygen is used.

The silicon oxide layer containing excess oxygen means a silicon oxidelayer from which oxygen can be released by heat treatment or the like.An insulating film containing excess oxygen means an insulating filmfrom which oxygen is released by heat treatment.

The insulating film containing excess oxygen is capable of reducingoxygen vacancies in the oxide semiconductor layer 306 a. Oxygenvacancies in the oxide semiconductor layer 306 a form defect states, andsome of the defect states become donor states. Thus, by a reduction inthe oxygen vacancies in the oxide semiconductor layer 306 a, thetransistor can have stable electrical characteristics.

Here, a layer from which oxygen is released by heat treatment mayrelease oxygen, the amount of which is higher than or equal to 1×10¹⁸atoms/cm³, higher than or equal to 1×10¹⁹ atoms/cm³, or higher than orequal to 1×10²⁰ atoms/cm³ in TDS analysis (converted into the number ofoxygen atoms).

Here, the method for measuring the amount of released oxygen using TDSanalysis is described below.

The total amount of released gas from a measurement sample in TDS isproportional to the integral value of the ion intensity of the releasedgas. Then, a comparison with a reference sample is made, whereby thetotal amount of released gas can be calculated.

For example, the number of released oxygen molecules (N_(O2)) from ameasurement sample can be calculated according to Formula 1 using theTDS results of a silicon wafer containing hydrogen at a predetermineddensity, which is a reference sample, and the TDS results of themeasurement sample. Here, all gases having a mass number of 32 which areobtained in the TDS analysis are assumed to originate from an oxygenmolecule. Note that CH₃OH, which is a gas having a mass number of 32, isnot taken into consideration because it is unlikely to be present.Further, an oxygen molecule including an oxygen atom having a massnumber of 17 or 18 which is an isotope of an oxygen atom is also nottaken into consideration because the proportion of such a molecule inthe natural world is minimal.

$\begin{matrix}{\lbrack {{FORMULA}\mspace{14mu} 1} \rbrack \mspace{580mu}} & \mspace{14mu} \\{N_{O\; 2} = {\frac{N_{H\; 2}}{S_{{H\; 2}\;}} \times S_{O\; 2} \times \alpha}} & (1)\end{matrix}$

Here, N_(H2) is the value obtained by conversion of the number ofhydrogen molecules desorbed from the reference sample into densities. Inaddition, S_(H2) is the integral value of ion intensity in the TDSanalysis of the reference sample. Here, the reference value of thereference sample is expressed as N_(H2)/S_(H2). Further, S_(O2) is theintegral value of ion intensity in the TDS analysis of the measurementsample, and a is a coefficient affecting the ion intensity in the TDSanalysis. For details of Formula 1, Japanese Published PatentApplication No. H6-275697 is referred to. The amount of released oxygenwas measured with a thermal desorption spectroscopy apparatus producedby ESCO Ltd., EMD-WA1000S/W using a silicon wafer containing hydrogenatoms at 1×10¹⁶ atoms/cm² as the reference sample.

Further, in the TDS analysis, oxygen is partly detected as an oxygenatom. The ratio between oxygen molecules and oxygen atoms can becalculated from the ionization rate of the oxygen molecules. Note that,since the above a includes the ionization rate of the oxygen molecules,the number of the released oxygen atoms can also be estimated throughthe evaluation of the number of the released oxygen molecules.

Note that N_(O2) is the number of the released oxygen molecules. Theamount of released oxygen when converted into oxygen atoms is twice thenumber of the released oxygen molecules.

Further, the layer from which oxygen is released by heat treatment maycontain a peroxide radical. Specifically, the spin density attributed toa peroxide radical is greater than or equal to 5×10¹⁷ spins/cm³. Notethat the layer containing a peroxide radical may have an asymmetricsignal at a g-factor of around 2.01 generated in ESR.

The insulating film containing excess oxygen may be oxygen-excesssilicon oxide (SiO_(X) (X>2)). In the oxygen-excess silicon oxide(SiO_(X) (X>2)), the number of oxygen atoms per unit volume is more thantwice the number of silicon atoms per unit volume. The number of siliconatoms and the number of oxygen atoms per unit volume are measured byRutherford backscattering spectrometry (RBS).

<2-1-4. Gate Insulating Film>

The gate insulating film 312 may be formed of a single layer or astacked layer using an insulating film containing one or more kinds ofaluminum oxide, magnesium oxide, silicon oxide, silicon oxynitride,silicon nitride oxide, silicon nitride, gallium oxide, germanium oxide,yttrium oxide, zirconium oxide, lanthanum oxide, neodymium oxide,hafnium oxide, and tantalum oxide.

The gate insulating film 312 may be, for example, a multilayer filmincluding a silicon nitride layer as a first layer and a silicon oxidelayer as a second layer. In that case, the silicon oxide layer may be asilicon oxynitride layer. In addition, the silicon nitride layer may bea silicon nitride oxide layer. As the silicon oxide layer, a siliconoxide layer whose defect density is low is preferably used.Specifically, a silicon oxide layer whose spin density attributed to asignal with a g factor of 2.001 in ESR is lower than or equal to 3×10¹⁷spins/cm³, preferably lower than or equal to 5×10¹⁶ spins/cm³ is used.As the silicon oxide layer, a silicon oxide layer containing excessoxygen is preferably used. As the silicon nitride layer, a siliconnitride layer from which a hydrogen gas and an ammonia gas are lesslikely to be released is used. The amount of released hydrogen gas orammonia gas may be measured by TDS.

In the case where at least one of the gate insulating film 312 and theprotective insulating film 318 includes an insulating film containingexcess oxygen, oxygen vacancies in the oxide semiconductor layer 306 aare reduced, so that stable electrical characteristics of a transistorcan be achieved.

<2-1-5. Gate Electrode>

The gate electrode 304 may be formed using a single layer or a stackedlayer of a conductive film containing one or more kinds of aluminum,titanium, chromium, cobalt, nickel, copper, yttrium, zirconium,molybdenum, ruthenium, silver, tantalum, and tungsten.

<2-1-6. Substrate>

There is no particular limitation on the substrate 300. For example, aglass substrate, a ceramic substrate, a quartz substrate, or a sapphiresubstrate may be used as the substrate 300. Alternatively, a singlecrystal semiconductor substrate or a polycrystalline semiconductorsubstrate made of silicon, silicon carbide, or the like, a compoundsemiconductor substrate made of silicon germanium or the like, asilicon-on-insulator (SOI) substrate, or the like may be used as thesubstrate 300. Still alternatively, any of these substrates providedwith a semiconductor element may be used as the substrate 300.

In the case where a large glass substrate such as the 5th generation(1000 mm×1200 mm or 1300 mm×1500 mm), the 6th generation (1500 mm×1800mm), the 7th generation (1870 mm×2200 mm), the 8th generation (2200mm×2500 mm), the 9th generation (2400 mm×2800 mm), or the 10thgeneration (2880 mm×3130 mm) is used as the substrate 300, minuteprocessing is sometimes difficult due to shrinkage of the substrate 300caused by heat treatment or the like in a manufacturing process of asemiconductor device. Therefore, in the case where the above-describedlarge glass substrate is used as the substrate 300, a substrate which isunlikely to shrink through the heat treatment is preferably used. Forexample, as the substrate 300, it is possible to use a large glasssubstrate in which the amount of shrinkage after heat treatment which isperformed for one hour at 400° C., preferably 450° C., more preferably500° C. is less than or equal to 10 ppm, preferably less than or equalto 5 ppm, more preferably less than or equal to 3 ppm.

Further alternatively, a flexible substrate may be used as the substrate300. Note that as a method for forming a transistor over a flexiblesubstrate, there is also a method in which, after a transistor is formedover a non-flexible substrate, the transistor is separated from thenon-flexible substrate and transferred to the substrate 300 which is aflexible substrate. In that case, a separation layer is preferablyprovided between the non-flexible substrate and the transistor.

In the transistor described above, a channel is formed in the oxidesemiconductor layer 306 a; thus, the transistor has stable electricalcharacteristics and high field-effect mobility. Even when the sourceelectrode 316 a and the drain electrode 316 b are formed of a multilayerfilm including a layer containing copper, stable electricalcharacteristics can be obtained.

<2-2. Method for Manufacturing Transistor Structure (1)>

A method for manufacturing a transistor is described here with referenceto FIGS. 8A to 8C and FIGS. 9A and 9B.

First, the substrate 300 is prepared.

Then, a conductive film to be the gate electrode 304 is formed. Theconductive film to be the gate electrode 304 may be formed using any ofthe conductive films given as examples of the gate electrode 304 by asputtering method, a chemical vapor deposition (CVD) method, a molecularbeam epitaxy (MBE) method, an atomic layer deposition (ALD) method, or apulsed laser deposition (PLD) method.

Next, the conductive film to be the gate electrode 304 is partly etchedto form the gate electrode 304 (see FIG. 8A).

Next, the gate insulating film 312 is formed (see FIG. 8B). The gateinsulating film 312 may be formed in such a manner that any of theinsulating films given above as examples of the gate insulating film 312is formed by a sputtering method, a CVD method, an MBE method, an ALDmethod, or a PLD method.

Next, an oxide semiconductor layer to be the oxide semiconductor layer306 a is formed. Note that the oxide semiconductor layer 306 a is formedso as to be a CAAC-OS film, a microcrystalline film, or an amorphousfilm, for example. When the oxide semiconductor layer 306 a is theCAAC-OS film, the microcrystalline film, or the amorphous film, forexample, an oxide semiconductor layer to be the oxide semiconductorlayer 306 b is likely to be a CAAC-OS film.

Next, the oxide semiconductor layer to be the oxide semiconductor layer306 b is formed. As the oxide semiconductor layer to be the oxidesemiconductor layer 306 b, any of the oxide semiconductor layersmentioned above as the oxide semiconductor layer 306 b can be formed bya sputtering method, a CVD method, an MBE method, an ALD method, or aPLD method.

Note that when the oxide semiconductor layer to be the oxidesemiconductor layer 306 a and the oxide semiconductor layer to be theoxide semiconductor layer 306 b are formed successively without beingexposed to the air, impurities are less likely to be taken intointerfaces between the layers; thus, the density of defect states or thedensity of trap states in the oxide semiconductor layer to be the oxidesemiconductor layer 306 a and/or the oxide semiconductor layer to be theoxide semiconductor layer 306 b can be reduced in some cases.

Next, the oxide semiconductor layer to be the oxide semiconductor layer306 a and the oxide semiconductor layer to be the oxide semiconductorlayer 306 b are partly etched to form the multilayer film 306 includingthe oxide semiconductor layer 306 a and the oxide semiconductor layer306 b (see FIG. 8C).

Next, first heat treatment is preferably performed. The first heattreatment can be performed at a temperature higher than or equal to 250°C. and lower than or equal to 650° C., preferably higher than or equalto 300° C. and lower than or equal to 500° C. The first heat treatmentis performed in an inert gas atmosphere, an atmosphere containing anoxidizing gas at 10 ppm or more, 1% or more, or 10% or more, or underreduced pressure. Alternatively, the first heat treatment may beperformed in such a manner that heat treatment is performed in an inertgas atmosphere, and then another heat treatment is performed in anatmosphere containing an oxidizing gas at 10 ppm or more, 1% or more, or10% or more in order to compensate desorbed oxygen. By the first heattreatment, the crystallinity of the oxide semiconductor layer 306 a canbe improved, and in addition, impurities such as hydrogen and water canbe removed from the gate insulating film 312 and/or the multilayer film306. Moreover, by the first heat treatment, the density of defect statesor the density of trap states in the oxide semiconductor layer 306 aand/or the oxide semiconductor layer 306 b can be reduced. Accordingly,treatment like the first heat treatment sometimes can be calledtreatment for reducing the density of defect states or the density oftrap states in an oxide semiconductor layer.

Next, a conductive film to be the source electrode 316 a and the drainelectrode 316 b is formed. The conductive film to be the sourceelectrode 316 a and the drain electrode 316 b may be formed in such amanner that any of the conductive films given above as examples of thesource electrode 316 a and the drain electrode 316 b is formed by asputtering method, a CVD method, an MBE method, an ALD method, or a PLDmethod.

For example, a multilayer film including a tungsten layer and a copperlayer over the tungsten layer may be formed as the conductive film to bethe source electrode 316 a and the drain electrode 316 b.

Next, the conductive film to be the source electrode 316 a and the drainelectrode 316 b is partly etched to form the source electrode 316 a andthe drain electrode 316 b (see FIG. 9A). In the case where a multilayerfilm including a tungsten layer and a copper layer over the tungstenlayer is used as the conductive film to be the source electrode 316 aand the drain electrode 316 b, the multilayer film can be etched withthe use of one photomask. Even when the tungsten layer and the copperlayer are etched at once, the concentration of copper in a regionbetween the oxide semiconductor layer 306 a and the oxide semiconductorlayer 306 b can be lower than 1×10¹⁹ atoms/cm³, lower than 2×10¹⁸atoms/cm³, or lower than 2×10¹⁷ atoms/cm³ owing to the oxidesemiconductor layer 306 b provided over the oxide semiconductor layer306 a; thus, an increase in the density of defect states or the densityof trap states in the oxide semiconductor layer 306 a and/or the oxidesemiconductor layer 306 b due to copper can be prevented. Consequently,deterioration of the electrical characteristics of the transistor can bereduced. Thus, the degree of freedom of the process is increased, sothat transistors can be manufactured with improved productivity.

Note that a defect state or a trap state is likely to be formed in themultilayer film 306 when the conductive film to be the source electrode316 a and the drain electrode 316 b is partly etched.

Next, second heat treatment is preferably performed. The description ofthe first heat treatment can be referred to for the second heattreatment. By the second heat treatment, impurities such as hydrogen andwater can be removed from the multilayer film 306. Hydrogen easily movesespecially in the multilayer film 306; thus, reducing hydrogen by thesecond heat treatment enables a reduction in the density of defectstates or the density of trap states in the oxide semiconductor layer306 a and/or the oxide semiconductor layer 306 b. Accordingly, thetransistor can have stable electrical characteristics. Note that wateris a compound containing hydrogen and thus may act as impurities in theoxide semiconductor layer 306 a.

Next, the protective insulating film 318 is formed (see FIG. 9B). Theprotective insulating film 318 may be formed in such a manner that anyof the insulating films given above as examples of the protectiveinsulating film 318 is formed by a sputtering method, a CVD method, anMBE method, an ALD method, or a PLD method.

Here, the case where the protective insulating film 318 has athree-layer structure as illustrated in FIG. 7D is described. First, thefirst silicon oxide layer 318 a is formed, and then the second siliconoxide layer 318 b is formed. Next, treatment for adding oxygen ions tothe first silicon oxide layer 318 a and/or the second silicon oxidelayer 318 b may be performed. The treatment for adding oxygen ions maybe performed with an ion doping apparatus or a plasma treatmentapparatus. As the ion doping apparatus, an ion doping apparatus with amass separation function may be used. As a source material of oxygenions, an oxygen gas such as ¹⁶O₂ or ¹⁸O₂, a nitrous oxide gas, an ozonegas, or the like may be used. Next, the silicon nitride layer 318 c isformed. The protective insulating film 318 may be formed in the abovemanner.

The first silicon oxide layer 318 a is preferably formed by a plasma CVDmethod which is one type of CVD method. Specifically, the first siliconoxide layer 318 a may be formed by supplying high-frequency power to anelectrode under the following conditions: the substrate temperature ishigher than or equal to 180° C. and lower than or equal to 400° C.,preferably higher than or equal to 200° C. and lower than or equal to370° C., a deposition gas containing silicon and an oxidizing gas areused, and the pressure is higher than or equal to 20 Pa and lower thanor equal to 250 Pa, preferably higher than or equal to 40 Pa and lowerthan or equal to 200 Pa. Note that typical examples of the depositiongas containing silicon include silane, disilane, trisilane, and silanefluoride. Examples of the oxidizing gas include oxygen, ozone, nitrousoxide, and nitrogen dioxide.

By setting the flow rate of the oxidizing gas to 100 times or more theflow rate of the deposition gas containing silicon, the hydrogen contentin the first silicon oxide layer 318 a can be reduced and dangling bondscan be reduced.

In the above manner, the first silicon oxide layer 318 a with a lowdefect density is formed. That is, the spin density of the first siliconoxide layer 318 a, which is attributed to a signal with a g factor of2.001 in ESR, can be lower than or equal to 3×10¹⁷ spins/cm³ or lowerthan or equal to 5×10¹⁶ spins/cm³.

The second silicon oxide layer 318 b is preferably formed by a plasmaCVD method. Specifically, the second silicon oxide layer 318 b may beformed by supplying high-frequency power higher than or equal to 0.17W/cm² and lower than or equal to 0.5 W/cm², preferably higher than orequal to 0.25 W/cm² and lower than or equal to 0.35 W/cm², to anelectrode under the following conditions: the substrate temperature ishigher than or equal to 160° C. and lower than or equal to 350° C.,preferably higher than or equal to 180° C. and lower than or equal to260° C., a deposition gas containing silicon and an oxidizing gas areused, and the pressure is higher than or equal to 100 Pa and lower thanor equal to 250 Pa, preferably higher than or equal to 100 Pa and lowerthan or equal to 200 Pa.

By the above-described method, the decomposition efficiency of the gasin plasma is enhanced, oxygen radicals are increased, and oxidation ofthe gas is promoted; thus, the second silicon oxide layer 318 bcontaining excess oxygen can be formed.

The silicon nitride layer 318 c is preferably formed by a plasma CVDmethod. Specifically, the silicon nitride layer 318 c may be formed bysupplying high-frequency power under the following conditions: thesubstrate temperature is higher than or equal to 180° C. and lower thanor equal to 400° C., preferably higher than or equal to 200° C. andlower than or equal to 370° C., a deposition gas containing silicon, anitrogen gas, and an ammonia gas are used, and the pressure is higherthan or equal to 20 Pa and lower than or equal to 250 Pa, preferablyhigher than or equal to 40 Pa and lower than or equal to 200 Pa.

Note that the flow rate of the nitrogen gas is set to 5 times or moreand 50 times or less, preferably 10 times or more and 50 times or lessthe flow rate of the ammonia gas. The use of ammonia gas can promotedecomposition of the deposition gas containing silicon and the nitrogengas. This is because the ammonia gas is dissociated by plasma energy orheat energy, and energy generated by the dissociation contributes todecomposition of a bond of the deposition gas containing silicon and abond of the nitrogen gas.

Through the above method, the silicon nitride layer 318 c from which thehydrogen gas and the ammonia gas are less likely to be released can beformed. The silicon nitride layer 318 c has low hydrogen content, andthus is dense and does not transmit or hardly transmit hydrogen, water,and oxygen.

Note that a defect state or a trap state is likely to be formed in themultilayer film 306 when the protective insulating film 318 is formed.

Next, third heat treatment is preferably performed. The description ofthe first heat treatment can be referred to for the third heattreatment. By the third heat treatment, excess oxygen is released fromthe gate insulating film 312 and/or the protective insulating film 318;thus, the number of defect states or trap states due to oxygen vacanciesin the multilayer film 306 can be reduced in some cases. Note that inthe multilayer film 306, an oxygen vacancy captures an adjacent oxygenatom, so that the oxygen vacancy seems to move in some cases.

In the above manner, the BGTC transistor can be manufactured.

In the transistor, the multilayer film 306 has a low density of defectstates or trap states in at least the oxide semiconductor layer 306 aserving as a channel formation region; thus, the transistor has stableelectrical characteristics.

<2-3. Transistor Structure (2)>

In this section, a top-gate transistor is described. Here, a top-gatetop-contact (TGTC) transistor, which is one kind of top-gate transistor,is described with reference to FIGS. 10A to 10C.

FIGS. 10A to 10C are a top view and cross-sectional views of the TGTCtransistor. FIG. 10A is the top view of the transistor. FIG. 10B is thecross-sectional view taken along dashed-dotted line D1-D2 in FIG. 10A.FIG. 10C is the cross-sectional view taken along dashed-dotted lineD3-D4 in FIG. 10A.

The transistor illustrated in FIG. 10B includes a base insulating film402 over a substrate 400; a multilayer film 406 including an oxidesemiconductor layer 406 a over the base insulating film 402 and an oxidesemiconductor layer 406 b over the oxide semiconductor layer 406 a; asource electrode 416 a and a drain electrode 416 b over the baseinsulating film 402 and the multilayer film 406; a gate insulating film412 over the multilayer film 406, the source electrode 416 a, and thedrain electrode 416 b; a gate electrode 404 over the gate insulatingfilm 412; and a protective insulating film 418 over the gate insulatingfilm 412 and the gate electrode 404. Note that the transistor does notnecessarily include the base insulating film 402 and/or the protectiveinsulating film 418.

Depending on the kind of a conductive film used for the source electrode416 a and the drain electrode 416 b, oxygen is taken away from part ofthe oxide semiconductor layer 406 b, or a mixed layer is formed, so thata source region and a drain region are formed in the oxide semiconductorlayer 406 b.

In FIG. 10A, the distance between the source electrode 416 a and thedrain electrode 416 b in a region overlapping with the gate electrode404 is referred to as a channel length. Note that in the case where thetransistor includes the source region and the drain region, the distancebetween the source region and the drain region in the region overlappingwith the gate electrode 404 may be referred to as a channel length.

Note that a channel formation region refers to a region which overlapswith the gate electrode 404 and is located between the source electrode416 a and the drain electrode 416 b in the multilayer film 406. Further,a channel region refers to a region through which current mainly flowsin the channel formation region. Here, the channel region is a portionof the oxide semiconductor layer 406 b in the channel formation region.

For the multilayer film 406, the description of the multilayer film 306is referred to. For example, for the oxide semiconductor layer 406 a,the description of the oxide semiconductor layer 306 b is referred to,and for the oxide semiconductor layer 406 b, the description of theoxide semiconductor layer 306 a is referred to.

For the substrate 400, the description of the substrate 300 is referredto. For the source electrode 416 a and the drain electrode 416 b,description of the source electrode 316 a and the drain electrode 316 bis referred to. For the gate insulating film 412, the description of thegate insulating film 312 is referred to. For the gate electrode 404, thedescription of the gate electrode 304 is referred to. For the protectiveinsulating film 418, the description of the protective insulating film318 is referred to.

Although the multilayer film 406 is covered with the gate electrode 404,the source electrode 416 a, and the drain electrode 416 b in FIG. 10A inorder to suppress generation of carriers in the multilayer film 406 dueto light, the multilayer film 406 is not necessarily covered with thegate electrode 404, the source electrode 416 a, and the drain electrode416 b.

The base insulating film 402 may be formed of a single layer or astacked layer using an insulating film containing one or more kinds ofaluminum oxide, magnesium oxide, silicon oxide, silicon oxynitride,silicon nitride oxide, silicon nitride, gallium oxide, germanium oxide,yttrium oxide, zirconium oxide, lanthanum oxide, neodymium oxide,hafnium oxide, and tantalum oxide.

The base insulating film 402 may be, for example, a multilayer filmincluding a silicon nitride layer as a first layer and a silicon oxidelayer as a second layer. In that case, the silicon oxide layer may be asilicon oxynitride layer. In addition, the silicon nitride layer may bea silicon nitride oxide layer. As the silicon oxide layer, a siliconoxide layer whose defect density is low is preferably used.Specifically, a silicon oxide layer whose spin density attributed to asignal with a g factor of 2.001 in ESR is lower than or equal to 3×10¹⁷spins/cm³, preferably lower than or equal to 5×10¹⁶ spins/cm³ is used.As the silicon nitride layer, a silicon nitride layer from whichhydrogen and ammonia are less likely to be released is used. The amountof released hydrogen or ammonia may be measured by TDS. Further, as thesilicon nitride layer, a silicon nitride layer which does not transmitor hardly transmits hydrogen, water, and oxygen is used.

The base insulating film 402 may be, for example, a multilayer filmincluding a silicon nitride layer as a first layer, a first siliconoxide layer as a second layer, and a second silicon oxide layer as athird layer. In that case, the first silicon oxide layer and/or thesecond silicon oxide layer may be a silicon oxynitride layer. Inaddition, the silicon nitride layer may be a silicon nitride oxidelayer. As the first silicon oxide layer, a silicon oxide layer whosedefect density is low is preferably used. Specifically, a silicon oxidelayer whose spin density attributed to a signal with a g factor of 2.001in ESR is lower than or equal to 3×10¹⁷ spins/cm³, preferably lower thanor equal to 5×10¹⁶ spins/cm³ is used. As the second silicon oxide layer,a silicon oxide layer having excess oxygen is used. As the siliconnitride layer, a silicon nitride layer from which hydrogen and ammoniaare less likely to be released is used. Further, as the silicon nitridelayer, a silicon nitride layer which does not transmit or hardlytransmits hydrogen, water, and oxygen is used.

In the case where at least one of the gate insulating film 412 and thebase insulating film 402 contains excess oxygen, the density of defectstates or trap states due to oxygen vacancies or the like in the oxidesemiconductor layer 406 b can be reduced.

In the above-described transistor, the channel is formed in the oxidesemiconductor layer 406 b of the multilayer film 406; thus, thetransistor has stable electrical characteristics and high field-effectmobility.

<2-4. Method for Manufacturing Transistor Structure (2)>

A method for manufacturing the transistor is described here withreference to FIGS. 11A to 11C and FIGS. 12A and 12B.

First, the substrate 400 is prepared.

Next, an oxide semiconductor layer to be the oxide semiconductor layer406 a is formed. For the method for forming the oxide semiconductorlayer to be the oxide semiconductor layer 406 a, the description of themethod for forming the oxide semiconductor layer 306 b is referred to.Note that the oxide semiconductor layer 406 a is formed so as to be aCAAC-OS film, a microcrystalline film, or an amorphous film. When theoxide semiconductor layer 406 a is the CAAC-OS film, themicrocrystalline film, or the amorphous film, an oxide semiconductorlayer to be the oxide semiconductor layer 406 b is likely to be aCAAC-OS film.

Next, an oxide semiconductor layer to be the oxide semiconductor layer406 b is formed. For the method for forming the oxide semiconductorlayer to be the oxide semiconductor layer 406 b, the description of themethod for forming the oxide semiconductor layer 306 a is referred to.

Next, first heat treatment is preferably performed. The first heattreatment can be performed at a temperature higher than or equal to 250°C. and lower than or equal to 650° C., preferably higher than or equalto 300° C. and lower than or equal to 500° C. The first heat treatmentis performed in an inert gas atmosphere, an atmosphere containing anoxidizing gas at 10 ppm or more, 1% or more, or 10% or more, or underreduced pressure. Alternatively, the first heat treatment may beperformed in such a manner that heat treatment is performed in an inertgas atmosphere, and then another heat treatment is performed in anatmosphere containing an oxidizing gas at 10 ppm or more, 1% or more, or10% or more in order to compensate desorbed oxygen. By the first heattreatment, the crystallinity of the oxide semiconductor layer to be theoxide semiconductor layer 406 b can be improved, and in addition,impurities such as hydrogen and water can be removed from the baseinsulating film 402, the oxide semiconductor layer to be the oxidesemiconductor layer 406 a, and/or the oxide semiconductor layer to bethe oxide semiconductor layer 406 b. Moreover, by the first heattreatment, the density of defect states or the density of trap states inthe oxide semiconductor layer 406 a and/or the oxide semiconductor layer406 b can be reduced. Accordingly, treatment like the first heattreatment sometimes can be called treatment for reducing the density ofdefect states or the density of trap states in an oxide semiconductorlayer.

Next, the oxide semiconductor layer to be the oxide semiconductor layer406 a and the oxide semiconductor layer to be the oxide semiconductorlayer 406 b are partly etched to form the multilayer film 406 includingthe oxide semiconductor layer 406 a and the oxide semiconductor layer406 b (see FIG. 11A).

Next, a conductive film to be the source electrode 416 a and the drainelectrode 416 b is formed. For the method for forming the conductivefilm to be the source electrode 416 a and the drain electrode 416 b, thedescription of the method for forming the conductive film to be thesource electrode 316 a and the drain electrode 316 b is referred to.

Next, the conductive film to be the source electrode 416 a and the drainelectrode 416 b is partly etched to form the source electrode 416 a andthe drain electrode 416 b (see FIG. 11B).

Note that a defect state or a trap state is likely to be formed in themultilayer film 406 when the conductive film to be the source electrode416 a and the drain electrode 416 b is partly etched.

Next, second heat treatment is preferably performed. The description ofthe first heat treatment can be referred to for the second heattreatment. By the second heat treatment, impurities such as hydrogen andwater can be removed from the multilayer film 406. Hydrogen easily movesespecially in the multilayer film 406; thus, reducing hydrogen by thesecond heat treatment enables a reduction in the density of defectstates or the density of trap states in the oxide semiconductor layer406 a and/or the oxide semiconductor layer 406 b. Accordingly, thetransistor can have stable electrical characteristics. Note that wateris a compound containing hydrogen and thus may act as impurities in theoxide semiconductor layer 406 a.

Next, the gate insulating film 412 is formed (see FIG. 11C). For themethod for forming the gate insulating film 412, the description of themethod for forming the gate insulating film 312 is referred to.

Note that a defect state or a trap state is likely to be formed in themultilayer film 406 when the gate insulating film 412 is formed.

Next, a conductive film to be the gate electrode 404 is formed. For themethod for forming the conductive film to be the gate electrode 404, thedescription of the method for forming the conductive film to be the gateelectrode 304 is referred to.

Next, the conductive film to be the gate electrode 404 is partly etchedto form the gate electrode 404 (see FIG. 12A).

Then, the protective insulating film 418 is formed (see FIG. 12B). Forthe method for forming the protective insulating film 418, thedescription of the method for forming the protective insulating film 318is referred to.

Next, third heat treatment is preferably performed. The description ofthe first heat treatment can be referred to for the third heattreatment. By the third heat treatment, excess oxygen is released fromat least one of the base insulating film 402, the gate insulating film412, and the protective insulating film 418; thus, the number of defectstates or trap states due to oxygen vacancies in the multilayer film 406can be reduced in some cases. Note that in the multilayer film 406, anoxygen vacancy captures an adjacent oxygen atom, so that the oxygenvacancy seems to move in some cases.

In the above manner, the TGTC transistor can be manufactured.

In the transistor, the multilayer film 406 has a low density of defectstates or trap states in at least the oxide semiconductor layer 406 bserving as a channel formation region; thus, the transistor has stableelectrical characteristics.

<3. Application Products>

Application products using the above transistor are described below.

<3-1. Display Device>

In this section, a display device to which the above transistor isapplied is described.

As a display element provided in the display device, a liquid crystalelement (also referred to as a liquid crystal display element), alight-emitting element (also referred to as a light-emitting displayelement), or the like can be used. A light-emitting element includes, inits category, an element whose luminance is controlled by current orvoltage, and specifically an inorganic electroluminescent (EL) element,an organic EL element, and the like. Furthermore, a display medium whosecontrast is changed by an electric effect, such as electronic ink or anelectrophoretic element, can be used as the display element. A displaydevice including an EL element and a display device including a liquidcrystal element are described below as examples of the display device.

The display device described below includes, in its category, a panel inwhich a display element is sealed and a module in which an IC such as acontroller is mounted on the panel.

The display device described below refers to an image display device ora light source (including a lighting device). The display deviceincludes any of the following modules in its category: a module providedwith a connector such as an FPC or TCP; a module in which a printedwiring board is provided at the end of TCP; and a module in which anintegrated circuit (IC) is mounted directly on a display element by aCOG method.

<3-1-1. EL Display Device>

First, a display device including an EL element (also called an ELdisplay device) is described.

FIG. 13 is an example of a circuit diagram of a pixel in the EL displaydevice.

Note that in this specification and the like, it might be possible forthose skilled in the art to constitute one embodiment of the inventioneven when portions to which all the terminals of an active element(e.g., a transistor or a diode), a passive element (e.g., a capacitor ora resistor), or the like are connected are not specified. In otherwords, even when such portions are not specified, one embodiment of thepresent invention can be clear and it can be determined that oneembodiment of the present invention is disclosed in this specificationand the like in some cases. In particular, in the case where the numberof portions to which the terminal is connected might be plural, it isnot necessary to specify the portions to which the terminal isconnected. Therefore, it might be possible to constitute one embodimentof the invention by specifying only portions to which some of terminalsof an active element (e.g., a transistor or a diode), a passive element(e.g., a capacitor or a resistor), or the like are connected.

Note that in this specification and the like, it might be possible forthose skilled in the art to specify the invention when at least theconnection portion of a circuit is specified. Alternatively, it might bepossible for those skilled in the art to specify the invention when atleast a function of a circuit is specified. In other words, when afunction of a circuit is specified, one embodiment of the presentinvention can be clear and it can be determined that one embodiment ofthe present invention is disclosed in this specification and the like insome cases. Therefore, when a connection portion of a circuit isspecified, the circuit is disclosed as one embodiment of the inventioneven when a function of the circuit is not specified, and one embodimentof the invention can be constituted. Alternatively, when a function of acircuit is specified, the circuit is disclosed as one embodiment of theinvention even when a connection portion of the circuit is notspecified, and one embodiment of the invention can be constituted.

The EL display device illustrated in FIG. 13 includes a switchingelement 743, a transistor 741, a capacitor 742, and a light-emittingelement 719.

Note that FIG. 13 and the like each illustrate an example of a circuitconfiguration; thus, a transistor can be provided additionally. On theother hand, for each node in FIG. 13, it is also possible not to providean additional transistor, switch, passive element, or the like. Forexample, it is possible not to increase the number of transistorsdirectly connected to the node A, the node B, the node C, the node D,the node E, the node F, and/or the node G. Accordingly, for example, thefollowing structure can be used: only the transistor 741 is directlyconnected to the node C and the other transistors are not directlyconnected to the node C.

A gate of the transistor 741 is electrically connected to one terminalof the switching element 743 and one terminal of the capacitor 742. Asource of the transistor 741 is electrically connected to one terminalof the light-emitting element 719. A drain of the transistor 741 iselectrically connected to the other terminal of the capacitor 742 and issupplied with a power supply potential VDD. The other terminal of theswitching element 743 is electrically connected to a signal line 744.The other terminal of the light-emitting element 719 is supplied with afixed potential. Note that the fixed potential is a ground potential GNDor lower.

Note that as the transistor 741, any of the above transistors each ofwhich includes the multilayer film including the oxide semiconductorlayer is used. The transistor has stable electrical characteristics.Thus, the EL display device can have high display quality.

As the switching element 743, a transistor is preferably used. When thetransistor is used as the switching element, the area of a pixel can bereduced, so that the EL display device can have high resolution. Any ofthe above transistors each of which includes the multilayer filmincluding the oxide semiconductor layer may be used as the switchingelement 743. When any of the above transistors is used as the switchingelement 743, the switching element 743 can be formed in the same processas the transistor 741, so that the productivity of the EL display devicecan be improved.

FIG. 14A is a top view of an EL display device. The EL display deviceincludes the substrate 300, a substrate 700, a sealant 734, a drivercircuit 735, a driver circuit 736, a pixel 737, and an FPC 732. Thesealant 734 is provided between the substrate 300 and the substrate 700so as to surround the pixel 737, the driver circuit 735, and the drivercircuit 736. Note that the driver circuit 735 and/or the driver circuit736 may be provided outside the sealant 734.

FIG. 14B is a cross-sectional view of the EL display device taken alongdashed-dotted line M-N in FIG. 14A. The FPC 732 is connected to a wiring733 a via a terminal 731. Note that the wiring 733 a is formed in thesame layer as the gate electrode 304.

Note that FIG. 14B shows an example in which the transistor 741 and thecapacitor 742 are provided in the same plane. With such a structure, thecapacitor 742 can be formed in the same plane as a gate electrode, agate insulating film, and a source electrode (drain electrode), whichare included in the transistor 741. When the transistor 741 and thecapacitor 742 are provided in the same plane in this manner, the numberof manufacturing steps of the EL display device can be reduced; thus,the productivity can be improved.

FIG. 14B illustrates an example in which the transistor illustrated inFIGS. 7A to 7D is used as the transistor 741. Therefore, for componentsof the transistor 741 which are not particularly described below, thedescription on FIGS. 7A to 7D is referred to.

An insulating film 720 is provided over the transistor 741 and thecapacitor 742.

Here, an opening reaching the source electrode 316 a of the transistor741 is provided in the insulating film 720 and the protective insulatingfilm 318.

An electrode 781 is provided over the insulating film 720. The electrode781 is connected to the source electrode 316 a of the transistor 741through the opening provided in the insulating film 720 and theprotective insulating film 318.

A partition 784 having an opening reaching the electrode 781 is providedover the electrode 781.

A light-emitting layer 782 in contact with the electrode 781 through theopening provided in the partition 784 is provided over the partition784.

An electrode 783 is provided over the light-emitting layer 782.

A region where the electrode 781, the light-emitting layer 782, and theelectrode 783 overlap with one another serves as the light-emittingelement 719.

Note that for the insulating film 720, the description of the protectiveinsulating film 318 is referred to. Alternatively, a resin film of apolyimide resin, an acrylic resin, an epoxy resin, a silicone resin, orthe like may be used.

The light-emitting layer 782 is not limited to a single layer, and maybe a stack of plural kinds of light-emitting layers and the like. Forexample, a structure illustrated in FIG. 14C may be employed. FIG. 14Cillustrates a structure in which an intermediate layer 785 a, alight-emitting layer 786 a, an intermediate layer 785 b, alight-emitting layer 786 b, an intermediate layer 785 c, alight-emitting layer 786 c, and an intermediate layer 785 d are stackedin this order. In that case, when light-emitting layers emitting lightof appropriate colors are used as the light-emitting layer 786 a, thelight-emitting layer 786 b, and the light-emitting layer 786 c, thelight-emitting element 719 with a high color rendering property orhigher emission efficiency can be formed.

Plural kinds of light-emitting layers may be stacked to obtain whitelight. Although not illustrated in FIG. 14B, white light may beextracted through coloring layers.

Although the structure in which three light-emitting layers and fourintermediate layers are provided is shown here, the structure is notlimited thereto. The number of light-emitting layers and the number ofintermediate layers can be changed as appropriate. For example, thelight-emitting layer 782 can be formed with only the intermediate layer785 a, the light-emitting layer 786 a, the intermediate layer 785 b, thelight-emitting layer 786 b, and the intermediate layer 785 c.Alternatively, the light-emitting layer 782 may be formed with theintermediate layer 785 a, the light-emitting layer 786 a, theintermediate layer 785 b, the light-emitting layer 786 b, thelight-emitting layer 786 c, and the intermediate layer 785 d; theintermediate layer 785 c may be omitted.

Further, the intermediate layer may have a stacked-layer structureincluding a hole-injection layer, a hole-transport layer, anelectron-transport layer, an electron-injection layer, or the like. Notethat not all of these layers need to be provided as the intermediatelayer. Any of these layers may be selected as appropriate to form theintermediate layer. Note that layers having similar functions may beprovided. Further, an electron-relay layer or the like may be added asappropriate as the intermediate layer, in addition to a carriergeneration layer.

The electrode 781 can be formed using a conductive film having visiblelight permeability. Having visible light permeability means to have anaverage transmittance of 70% or more, particularly 80% or more in thevisible light region (e.g., the range of wavelength of from 400 nm to800 nm).

As the electrode 781, for example, an oxide film such as an In—Zn—Woxide film, an In—Sn oxide film, an In—Zn oxide film, an indium oxidefilm, a zinc oxide film, or a tin oxide film may be used. The aboveoxide film may contain a minute amount of Al, Ga, Sb, F, or the like.Further, a metal thin film having a thickness which enables light to betransmitted (preferably, approximately 5 nm to 30 nm) can also be used.For example, an Ag film, a Mg film, or an Ag—Mg alloy film with athickness of 5 nm may be used.

Alternatively, the electrode 781 is preferably a film which efficientlyreflects visible light. For example, a film containing lithium,aluminum, titanium, magnesium, lanthanum, silver, silicon, or nickel canbe used as the electrode 781.

The electrode 783 can be formed using any of the films for the electrode781. Note that when the electrode 781 has visible light permeability, itis preferable that the electrode 783 efficiently reflects visible light.When the electrode 781 efficiently reflects visible light, it ispreferable that the electrode 783 have visible light permeability.

Positions of the electrode 781 and the electrode 783 are not limited tothe structure illustrated in FIG. 14B, and the electrode 781 and theelectrode 783 may be replaced with each other. It is preferable to use aconductive film having a high work function for the electrode whichserves as an anode and a conductive film having a low work function forthe electrode which serves as a cathode. Note that in the case where acarrier generation layer is provided in contact with the anode, avariety of conductive films can be used for the anode regardless oftheir work functions.

For the partition 784, the description of the protective insulating film318 is referred to. Alternatively, a resin film of a polyimide resin, anacrylic resin, an epoxy resin, a silicone resin, or the like may beused.

The transistor 741 connected to the light-emitting element 719 hasstable electrical characteristics. Thus, an EL display device havinghigh display quality can be provided.

FIGS. 15A and 15B each illustrate an example of a cross section of an ELdisplay device which is partly different from that in FIG. 14B.Specifically, the difference lies in a wiring connected to the FPC 732.In FIG. 15A, a wiring 733 b is connected to the FPC 732 via the terminal731. The wiring 733 b is formed in the same layer as the sourceelectrode 316 a and the drain electrode 316 b. In FIG. 15B, a wiring 733c is connected to the FPC 732 via the terminal 731. The wiring 733 c isformed in the same layer as the electrode 781.

<3-1-2. Liquid Crystal Display Device>

Next, a display device including a liquid crystal element (also called aliquid crystal display device) is described.

FIG. 16 is a circuit diagram showing a structural example of a pixel ofthe liquid crystal display device. A pixel 750 illustrated in FIG. 16includes a transistor 751, a capacitor 752, and an element in whichliquid crystal is injected between a pair of electrodes (hereinafteralso referred to as liquid crystal element) 753.

One of a source and a drain of the transistor 751 is electricallyconnected to a signal line 755, and a gate of the transistor 751 iselectrically connected to a scan line 754.

One of electrodes of the capacitor 752 is electrically connected to theother of the source and the drain of the transistor 751, and the otherof the electrodes of the capacitor 752 is electrically connected to awiring for supplying a common potential.

One of electrodes of the liquid crystal element 753 is electricallyconnected to the other of the source and the drain of the transistor751, and the other of the electrodes of the liquid crystal element 753is electrically connected to a wiring for supplying a common potential.Note that the common potential supplied to the other of the electrodesof the liquid crystal element 753 may be different from the commonpotential supplied to the wiring to which the other of the electrodes ofthe capacitor 752 is electrically connected.

Note that a top view of the liquid crystal display device is roughlysimilar to that of the EL display device. FIG. 17A is a cross-sectionalview of the liquid crystal display device taken along dashed-dotted lineM-N in FIG. 14A. In FIG. 17A, the FPC 732 is connected to the wiring 733a via the terminal 731. Note that the wiring 733 a is formed in the samelayer as the gate electrode 304.

Note that FIG. 17A illustrates an example in which the transistor 751and the capacitor 752 are provided in the same plane. With such astructure, the capacitor 752 can be formed in the same plane as a gateelectrode, a gate insulating film, and a source electrode (drainelectrode), which are included in the transistor 751. When thetransistor 751 and the capacitor 752 are provided in the same plane inthis manner, the number of manufacturing steps of the liquid crystaldisplay device can be reduced; thus, the productivity can be improved.

As the transistor 751, any of the above transistors can be used. In FIG.17A, the transistor illustrated in FIGS. 7A to 7D is used as thetransistor 751. Therefore, for components of the transistor 751 whichare not particularly described below, the description of FIGS. 7A to 7Dis referred to.

Note that the transistor 751 can be a transistor having extremely lowoff-state current. Thus, the charge held in the capacitor 752 isunlikely to leak and voltage applied to the liquid crystal element 753can be retained for a long time. Thus, by turning off the transistor 751when an image with little motion or a still image is displayed, powerfor the operation of the transistor 751 is not needed. As a result, thepower consumption of the liquid crystal display device can be low.

An insulating film 721 is provided over the transistor 751 and thecapacitor 752.

Here, an opening reaching the drain electrode 316 b of the transistor751 is provided in the insulating film 721 and the protective insulatingfilm 318.

An electrode 791 is provided over the insulating film 721. The electrode791 is in contact with the drain electrode 316 b of the transistor 751through the opening provided in the insulating film 721 and theprotective insulating film 318.

An insulating film 792 serving as an alignment film is provided over theelectrode 791.

A liquid crystal layer 793 is provided over the insulating film 792.

An insulating film 794 serving as an alignment film is provided over theliquid crystal layer 793.

A spacer 795 is provided over the insulating film 794.

An electrode 796 is provided over the spacer 795 and the insulating film794.

A substrate 797 is provided over the electrode 796.

For the insulating film 721, the description of the protectiveinsulating film 318 is referred to. Alternatively, a resin film of apolyimide resin, an acrylic resin, an epoxy resin, a silicone resin, orthe like may be used.

For the liquid crystal layer 793, a thermotropic liquid crystal, alow-molecular liquid crystal, a polymer liquid crystal, apolymer-dispersed liquid crystal, a ferroelectric liquid crystal, ananti-ferroelectric liquid crystal, or the like can be used. Such aliquid crystal material exhibits a cholesteric phase, a smectic phase, acubic phase, a chiral nematic phase, an isotropic phase, or the likedepending on conditions.

Note that as the liquid crystal layer 793, a liquid crystal exhibiting ablue phase may be used. In that case, the insulating films 792 and 794serving as alignment films are not necessarily provided.

The electrode 791 can be formed using a conductive film having visiblelight permeability.

As the electrode 791, for example, an oxide film such as an In—Zn—Woxide film, an In—Sn oxide film, an In—Zn oxide film, an indium oxidefilm, a zinc oxide film, or a tin oxide film may be used. The aboveoxide film may contain a minute amount of Al, Ga, Sb, F, or the like.Further, a metal thin film having a thickness which enables light to betransmitted (preferably, approximately 5 nm to 30 nm) can also be used.

Alternatively, the electrode 791 is preferably a film which efficientlyreflects visible light. For example, a film containing aluminum,titanium, chromium, copper, molybdenum, silver, tantalum, or tungstencan be used as the electrode 791.

The electrode 796 can be formed using any of the films for the electrode791. Note that when the electrode 791 has visible light permeability, itis preferable that the electrode 796 efficiently reflect visible light.When the electrode 791 efficiently reflects visible light, it ispreferable that the electrode 796 have visible light permeability.

Positions of the electrode 791 and the electrode 796 are not limited tothe structure illustrated in FIG. 17A, and the electrode 791 and theelectrode 796 may be replaced with each other.

Each of the insulating films 792 and 794 may be formed using an organiccompound or an inorganic compound.

The spacer 795 may be formed using an organic compound or an inorganiccompound. Note that the spacer 795 can have a variety of shapes such asa columnar shape and a spherical shape.

A region where the electrode 791, the insulating film 792, the liquidcrystal layer 793, the insulating film 794, and the electrode 796overlap with one another functions as the liquid crystal element 753.

As the substrate 797, a glass substrate, a resin substrate, a metalsubstrate, or the like can be used. The substrate 797 may haveflexibility.

FIGS. 17B and 17C each illustrate an example of a cross section of aliquid crystal display device which is partly different from that inFIG. 17A. Specifically, the difference lies in a wiring connected to theFPC 732. In FIG. 17B, the wiring 733 b is connected to the FPC 732 viathe terminal 731. The wiring 733 b is formed in the same layer as thesource electrode 316 a and the drain electrode 316 b. In FIG. 17C, thewiring 733 c is connected to the FPC 732 via the terminal 731. Thewiring 733 c is formed in the same layer as the electrode 791.

The transistor 751 connected to the liquid crystal element 753 hasstable electrical characteristics. Thus, a liquid crystal display devicehaving high display quality can be provided. Further, since theoff-state current of the transistor 751 can be extremely low, a displaydevice with low power consumption can be provided.

Operation modes of liquid crystal is described below, using examples.Driving methods of a liquid crystal of a liquid crystal display deviceinclude a vertical electric field method where voltage is appliedperpendicular to a substrate and a horizontal electric field methodwhere voltage is applied in parallel to a substrate.

First, FIGS. 18A1 and 18A2 are cross-sectional schematic viewsillustrating a pixel structure of a TN-mode liquid crystal displaydevice.

A liquid crystal layer 3100 is held between a substrate 3101 and asubstrate 3102 which are arranged so as to face each other. A polarizingplate 3103 is formed on the substrate 3101 side and a polarizing plate3104 is formed on the substrate 3102 side. The absorption axis of thepolarizing plate 3103 and the absorption axis of the polarizing plate3104 are arranged in a cross-Nicol state.

Although not illustrated, a backlight and the like are provided outsidethe polarizing plate 3104. An electrode 3108 and an electrode 3109 areprovided on the substrate 3101 and the substrate 3102, respectively. Theelectrode 3108 on the opposite side to the backlight, that is, on theviewing side, is formed to have a light-transmitting property.

In the case where a liquid crystal display device having such astructure is in a normally white mode, when voltage is applied betweenthe electrode 3108 and the electrode 3109 (referred to as a verticalelectric field method), liquid crystal molecules 3105 are alignedvertically as illustrated in FIG. 18A1. Thus, the light from thebacklight cannot pass through the polarizing plate 3103, which leads toblack display.

When no voltage is applied between the electrode 3108 and the electrode3109, the liquid crystal molecules 3105 are aligned horizontally andtwisted on a plane surface as illustrated in FIG. 18A2. As a result,light from the backlight can pass through the polarizing plate 3103,which leads to white display. In addition, the gray scale can beexpressed by adjusting the voltage applied between the electrode 3108and the electrode 3109. In this manner, a predetermined image isdisplayed.

At this time, full color display can be performed by providing acoloring layer. The coloring layer can be provided on either thesubstrate 3101 side or on the substrate 3102 side.

A known liquid crystal molecule may be used as a liquid crystal materialfor the TN mode.

FIGS. 18B1 and 18B2 are cross-sectional schematic views illustrating apixel structure of a VA-mode liquid crystal display device. In the VAmode, the liquid crystal molecules 3105 are aligned such that they areperpendicular to the substrate when there is no electric field.

As in FIGS. 18A1 and 18A2, the electrode 3108 and the electrode 3109 areprovided on the substrate 3101 and the substrate 3102, respectively. Theelectrode 3108 on the opposite side to the backlight, that is, on theviewing side, is formed to have a light-transmitting property. Thepolarizing plate 3103 is formed on the substrate 3101 side, and thepolarizing plate 3104 is formed on the substrate 3102 side. Theabsorption axis of the polarizing plate 3103 and the absorption axis ofthe polarizing plate 3104 are arranged in a cross-Nicol state.

When voltage is applied between the electrode 3108 and the electrode3109 (the vertical electric field method) in a liquid crystal displaydevice having such a structure, the liquid crystal molecules 3105 arealigned horizontally as illustrated in FIG. 18B1. Thus, light from thebacklight can pass through the polarizing plate 3103, which leads towhite display.

When no voltage is applied between the electrode 3108 and the electrode3109, the liquid crystal molecules 3105 are aligned vertically asillustrated in FIG. 18B2. As a result, light from the backlight which ispolarized by the polarizing plate 3104 passes through a cell withoutbeing influenced by birefringence of the liquid crystal molecules 3105.Thus, the light from the backlight which is polarized cannot passthrough the polarizing plate 3103, which leads to black display. Inaddition, the gray scale can be expressed by adjusting the voltageapplied between the electrode 3108 and the electrode 3109. In thismanner, a predetermined image is displayed.

At this time, full color display can be performed by providing acoloring layer. The coloring layer can be provided on either thesubstrate 3101 side or on the substrate 3102 side.

FIGS. 18C1 and 18C2 are cross-sectional schematic views illustrating apixel structure of an MVA-mode liquid crystal display device. The MVAmode is a method in which one pixel is divided into a plurality ofportions, and the portions have different alignment directions of theliquid crystal molecules 3105 and compensate the viewing angledependencies with each other. As illustrated in FIG. 18C1, in the MVAmode, a protrusion 3158 whose cross section is a triangle is provided onthe electrode 3108 and a protrusion 3159 whose cross section is atriangle is provided on the electrode 3109 for controlling alignment.Note that the other structures are similar to those of the VA mode.

When voltage is applied between the electrode 3108 and the electrode3109 (the vertical electric field method), the liquid crystal molecules3105 are aligned so that a long axis of the liquid crystal molecule 3105is substantially vertical to surfaces of the protrusions 3158 and 3159as illustrated in FIG. 18C1. Thus, light from the backlight can passthrough the polarizing plate 3103, which leads to white display.

When no voltage is applied between the electrode 3108 and the electrode3109, the liquid crystal molecules 3105 are aligned vertically asillustrated in FIG. 18C2. As a result, light from the backlight cannotpass through the polarizing plate 3103, which leads to black display. Inaddition, the gray scale can be expressed by adjusting the voltageapplied between the electrode 3108 and the electrode 3109. In thismanner, a predetermined image is displayed.

At this time, full color display can be performed by providing acoloring layer. The coloring layer can be provided on either thesubstrate 3101 side or on the substrate 3102 side.

FIGS. 21A and 21B are a top view and a cross-sectional view,respectively, of another example of the MVA mode. As illustrated in FIG.21A, an electrode 3109 a, an electrode 3109 b, and an electrode 3109 care each formed into a bent pattern like a dogleg-like shape (V-likeshape). As illustrated in FIG. 21B, an insulating film 3162 and aninsulating film 3163 which function as alignment films are formed overthe electrodes 3109 a, 3109 b, and 3109 c and over the electrode 3108,respectively. The protrusion 3158 is formed on the electrode 3108 so asto overlap with the electrode 3109 b.

FIGS. 19A1 and 19A2 are cross-sectional schematic views illustrating apixel structure of an OCB-mode liquid crystal display device. In the OCBmode, the liquid crystal molecules 3105 in a liquid crystal layer arealigned so that they compensate the viewing angle dependence. Thisalignment is called a bend alignment.

As in FIGS. 18A1 to 18C2, the electrode 3108 is provided on thesubstrate 3101 and the electrode 3109 is provided on the substrate 3102.The electrode 3108 on the opposite side to the backlight, that is, onthe viewing side, is formed to have a light-transmitting property. Thepolarizing plate 3103 is formed on the substrate 3101 side, and thepolarizing plate 3104 is formed on the substrate 3102 side. Theabsorption axis of the polarizing plate 3103 and the absorption axis ofthe polarizing plate 3104 are arranged in a cross-Nicol state.

When voltage is applied between the electrode 3108 and the electrode3109 (the vertical electric field method) in a liquid crystal displaydevice having such a structure, black display is performed. At thistime, the liquid crystal molecules 3105 are aligned vertically asillustrated in FIG. 19A1. Thus, the light from the backlight cannot passthrough the polarizing plate 3103, which leads to black display.

When no voltage is applied between the electrode 3108 and the electrode3109, the liquid crystal molecules 3105 exist in a bend alignment stateas illustrated in FIG. 19A2. As a result, light from the backlight canpass through the polarizing plate 3103, which leads to white display. Inaddition, the gray scale can be expressed by adjusting the voltageapplied between the electrode 3108 and the electrode 3109. In thismanner, a predetermined image is displayed.

At this time, full color display can be performed by providing acoloring layer. The coloring layer can be provided on either thesubstrate 3101 side or on the substrate 3102 side.

In such an OCB mode, alignment of the liquid crystal molecules 3105 cancompensate the viewing angle dependence. In addition, a contrast ratiocan be increased by a pair of stacked layers including polarizers.

FIGS. 19B1 and 19B2 are cross-sectional schematic views illustratingpixel structures of an FLC-mode liquid crystal display device or anAFLC-mode liquid crystal display device.

As in FIGS. 18A1 to 18C2, the electrode 3108 is provided on thesubstrate 3101 and the electrode 3109 is provided on the substrate 3102.The electrode 3108 on the opposite side to the backlight, that is, onthe viewing side, is formed to have a light-transmitting property. Thepolarizing plate 3103 is formed on the substrate 3101 side, and thepolarizing plate 3104 is formed on the substrate 3102 side. Theabsorption axis of the polarizing plate 3103 and the absorption axis ofthe polarizing plate 3104 are arranged in a cross-Nicol state.

In the liquid crystal display device having such a structure, whenvoltage is applied between the electrode 3108 and the electrode 3109(referred to as vertical electric field method), the liquid crystalmolecules 3105 are aligned horizontally in a direction deviated from arubbing direction as illustrated in FIG. 19B1. As a result, light fromthe backlight can pass through the polarizing plate 3103, which leads towhite display.

When no voltage is applied between the electrode 3108 and the electrode3109, the liquid crystal molecules 3105 are aligned horizontally alongthe rubbing direction as illustrated in FIG. 19B2. Thus, the light fromthe backlight cannot pass through the polarizing plate 3103, which leadsto black display. In addition, the gray scale can be expressed byadjusting the voltage applied between the electrode 3108 and theelectrode 3109. In this manner, a predetermined image is displayed.

At this time, full color display can be performed by providing acoloring layer. The coloring layer can be provided on either thesubstrate 3101 side or on the substrate 3102 side.

A known liquid crystal molecule may be used for the FLC-mode liquidcrystal display device or the AFLC-mode liquid crystal display device.

FIGS. 20A1 and 20A2 are cross-sectional schematic views illustrating apixel structure of an IPS-mode liquid crystal display device. The IPSmode is a mode in which the liquid crystal molecules 3105 are rotated ina plane parallel to a substrate by horizontal electric field generatedby the electrodes provided for only one substrate side.

The IPS mode is characterized in that liquid crystals are controlled bya pair of electrodes which are provided on one substrate. Thus, a pairof electrodes 3150 and 3151 are provided over the substrate 3102. Thepair of electrodes 3150 and 3151 each preferably have alight-transmitting property. The polarizing plate 3103 is formed on thesubstrate 3101 side, and the polarizing plate 3104 is formed on thesubstrate 3102 side. The absorption axis of the polarizing plate 3103and the absorption axis of the polarizing plate 3104 are arranged in across-Nicol state.

When voltage is applied between the pair of electrodes 3150 and 3151 inthe liquid crystal display device having such a structure, the liquidcrystal molecules 3105 are aligned along an electric flux line deviatedfrom a rubbing direction as illustrated in FIG. 20A1. Thus, light fromthe backlight can pass through the polarizing plate 3103, which leads towhite display.

When no voltage is applied between the pair of electrodes 3150 and 3151,the liquid crystal molecules 3105 are aligned horizontally along therubbing direction as illustrated in FIG. 20A2. As a result, light fromthe backlight cannot pass through the polarizing plate 3103, which leadsto black display. In addition, the grayscale can be expressed byadjusting the voltage applied between the pair of electrodes 3150 and3151. In this manner, a predetermined image is displayed.

At this time, full color display can be performed by providing acoloring layer. The coloring layer can be provided on either thesubstrate 3101 side or on the substrate 3102 side.

FIGS. 22A to 22C each illustrate an example of the pair of electrodes3150 and 3151 that can be used in the IPS mode. As illustrated in topviews of FIGS. 22A to 22C, the pair of electrodes 3150 and 3151 arearranged alternately. In FIG. 22A, electrodes 3150 a and 3151 a eachhave a wave-like shape. In FIG. 22B, electrodes 3150 b and 3151 b eachhave a comb-like shape and partly overlap with each other. In FIG. 22C,electrodes 3150 c and 3151 c have a comb-like shape in which theelectrodes are meshed with each other.

FIGS. 20B1 and 20B2 are cross-sectional schematic views illustrating apixel structure of an FFS-mode liquid crystal display device. The FFSmode is also a horizontal electric field method as in the IPS mode andhas a structure in which the electrode 3151 is formed over the electrode3150 with an insulating film 3154 provided therebetween as illustratedin FIGS. 20B 1 and 20B2.

The pair of electrodes 3150 and 3151 each preferably have alight-transmitting property. The polarizing plate 3103 is formed on thesubstrate 3101 side, and the polarizing plate 3104 is formed on thesubstrate 3102 side. The absorption axis of the polarizing plate 3103and the absorption axis of the polarizing plate 3104 are arranged in across-Nicol state.

When voltage is applied between the pair of electrodes 3150 and 3151 ina liquid crystal display device having such a structure, the liquidcrystal molecules 3105 are aligned along an electric flux line deviatedfrom a rubbing direction as illustrated in FIG. 20B1. Thus, light fromthe backlight can pass through the polarizing plate 3103, which leads towhite display.

When no voltage is applied between the pair of electrodes 3150 and 3151,the liquid crystal molecules 3105 are aligned horizontally along therubbing direction as illustrated in FIG. 20B2. As a result, light fromthe backlight cannot pass through the polarizing plate 3103, which leadsto black display. In addition, the grayscale can be expressed byadjusting the voltage applied between the pair of electrodes 3150 and3151. In this manner, a predetermined image is displayed.

At this time, full color display can be performed by providing acoloring layer. The coloring layer can be provided on either thesubstrate 3101 side or on the substrate 3102 side.

FIGS. 23A to 23C each show an example of the pair of electrodes 3150 and3151 that can be used in the FFS mode. As illustrated in top views ofFIGS. 23A to 23C, the electrodes 3151 are formed into various patternsover the electrodes 3150. In FIG. 23A, the electrode 3151 a over theelectrode 3150 a has a bent dogleg-like shape (V-like shape). In FIG.23B, the electrode 3151 b over the electrode 3150 b has a comb-likeshape in which the electrodes are meshed with each other. In FIG. 23C,the electrode 3151 c over the electrode 3150 c has a comb-like shape.

A known liquid crystal molecule may be used for the IPS-mode liquidcrystal display device and the FFS-mode liquid crystal display device.

Another operation mode such as a PVA mode, an ASM mode, or a IBA modemay be employed.

In the liquid crystal display device, a black matrix (a light-blockinglayer), an optical member (an optical substrate) such as a polarizingmember, a retardation member, or an anti-reflection member, and the likeare provided as appropriate. For example, circular polarization may beemployed by using a polarizing substrate and a retardation substrate. Inaddition, a backlight, a side light, or the like may be used as a lightsource.

In addition, it is possible to employ a time-division display method(field-sequential driving method) with the use of a plurality oflight-emitting diodes (LEDs) for a backlight. A field-sequential drivingmethod enables color display without using a coloring layer.

As a display method in the pixel portion, a progressive method, aninterlace method, or the like is employed. Further, color elementscontrolled in a pixel at the time of color display are not limited tothree colors: R, G, and B (R, G, and B correspond to red, green, andblue, respectively). For example, R, B, and W (W corresponds to white),or R, C, B, and one or more of yellow, cyan, magenta, and the like canbe used. Further, the sizes of display regions may be different betweenrespective dots of color elements. Note that one embodiment of thepresent invention is not limited to a color liquid crystal displaydevice and can be applied to a monochrome liquid crystal display device.

<3-2. Touch Sensor>

A structure example of a sensor that can sense proximity or a touch ofan object (hereinafter referred to as a touch sensor) which is oneembodiment of the present invention is described below.

For a touch sensor, a variety of types such as a capacitive type, aresistive type, a surface acoustic wave type, an infrared type, and anoptical type can be used.

Typical examples of a capacitive touch sensor are a surface capacitivetouch sensor and a projected capacitive touch sensor. Further, examplesof the projected capacitive touch sensor are a self capacitive touchsensor and a mutual capacitive touch sensor, which differ mainly in thedriving method. The use of a mutual capacitive touch sensor ispreferable because multiple points can be sensed simultaneously.

<3-2-1. Example of Detection Method of Touch Sensor>

FIGS. 24A and 24B are schematic diagrams each illustrating a structureof a mutual capacitive touch sensor and input and output waveforms. Thetouch sensor includes a pair of electrodes. Capacitance is formedbetween the pair of electrodes. Input voltage is input to one of thepair of electrodes. Further, a detection circuit which detects currentflowing in the other electrode (or a potential of the other electrode)is provided.

For example, in the case where a rectangular wave is used as an inputvoltage waveform as illustrated in FIG. 24A, a waveform having a sharppeak is detected as an output current waveform.

Further, in the case where a conductive object is close to or touches acapacitor as illustrated in FIG. 24B, the capacitance value between theelectrodes is decreased; accordingly, the value of output current isdecreased.

By detecting a change in capacitance by using a change in output current(or potential) with respect to input voltage in this manner, proximityor a touch of an object can be detected.

<3-2-2. Structure Example of Touch Sensor>

FIG. 24C illustrates a structure example of a touch sensor provided witha plurality of capacitors arranged in a matrix.

The touch sensor includes a plurality of wirings extending in the Xdirection (the horizontal direction of this figure) and a plurality ofwirings extending in the Y direction (the vertical direction of thisfigure) which intersect with the plurality of wirings. Capacitance isformed between two wirings intersecting with each other.

One of input voltage and a common potential (including a groundedpotential and a reference potential) is input to the wiring extending inthe X direction. Further, a detection circuit (e.g., a source meter or asense amplifier) is electrically connected to each of the wiringsextending in the Y direction and can detect current flowing through thewiring (or a potential of the wiring).

The touch sensor can perform sensing two dimensionally in such a mannerthat the touch sensor sequentially scans the plurality of wiringsextending in the X direction so that input voltage is input and detectsa change in current flowing through the wirings extending in the Ydirection (or potentials of the wirings).

<3-2-3. Structure Example of Touch Panel>

A structure example of a touch panel incorporating the touch sensor intoa display portion including a plurality of pixels is described below.Here, an example where a liquid crystal element is used as a displayelement provided in the pixel is shown. Note that an EL element may beused as the display element provided in the pixel.

FIG. 25A is an equivalent circuit diagram of part of a pixel circuitprovided in the display portion of the touch panel described in thisstructure example.

Each pixel includes at least a transistor 3503 and a liquid crystalelement 3504. In addition, a gate of the transistor 3503 is electricallyconnected to a wiring 3501, and one of a source and a drain of thetransistor 3503 is electrically connected to a wiring 3502.

The pixel circuit includes a plurality of wirings extending in the Xdirection (e.g., a wiring 3510_1 and a wiring 3510_2) and a plurality ofwirings extending in the Y direction (e.g., wirings 3511). These wiringsare provided to intersect with each other, and capacitance is formedtherebetween.

Among the pixels provided in the pixel circuit, ones of electrodes ofthe liquid crystal elements of some pixels adjacent to each other areelectrically connected to each other to form one block. The block isclassified into two types: an island-shaped block (e.g., a block 3515_1or a block 3515_2) and a linear block (e.g., a block 3516) extending inthe Y direction.

The wiring 3510_1 (or 3510_2) extending in the X direction iselectrically connected to the island-shaped block 3515_1 (or the block3515_2). Further, the wiring 3511 extending in the Y direction iselectrically connected to the linear block 3516.

FIG. 25B is an equivalent circuit diagram in which a plurality ofwirings 3510 extending in the X direction and the plurality of wirings3511 extending in the Y direction are illustrated. Input voltage or acommon potential can be input to each of the wirings 3510 extending inthe X direction. Further, a ground potential can be input to each of thewirings 3511 extending in the Y direction, or each of the wirings 3511can be electrically connected to a detection circuit.

<3-2-4. Operation Example of Touch Panel>

Operation of the above-described touch panel is described with referenceto FIGS. 26A and 26B and FIG. 27.

As illustrated in FIG. 27, one frame period is divided into a writingperiod and a detecting period. In the writing period, a period in whichimage data is written to a pixel, the wirings 3510 (also referred to asgate lines) are sequentially selected. In the detecting period, a periodin which sensing is performed by a touch sensor, the wirings 3510extending in the X direction are sequentially selected and input voltageis input.

FIG. 26A is an equivalent circuit diagram in the writing period. In thewriting period, a common potential is input to both the wiring 3510extending in the X direction and the wiring 3511 extending in the Ydirection.

FIG. 26B is an equivalent circuit diagram at some point in time in thedetection period. In the detection period, each of the wirings 3511extending in the Y direction is electrically connected to the detectioncircuit. Input voltage is input to the wirings 3510 extending in the Xdirection which are selected, and a common potential is input to thewirings 3510 extending in the X direction which are not selected.

It is preferable that a period in which an image is written and a periodin which sensing is performed by a touch sensor be separately providedas described above. Thus, a decrease in sensitivity of the touch sensorcaused by noise generated when data is written to a pixel can besuppressed.

<3-2-5. Structure Examples of Pixel>

Structure examples of a pixel which can be used for the above touchpanel are described below.

FIG. 28A is a cross-sectional schematic diagram illustrating part of apixel using an FFS mode of a liquid crystal display device.

The pixel includes a transistor 3521, an electrode 3522, an electrode3523, a liquid crystal 3524, and a color filter 3525. The electrode 3523having an opening is electrically connected to one of a source and adrain of the transistor 3521. The electrode 3523 is provided over theelectrode 3522 with an insulating film provided therebetween. Theelectrode 3523 and the electrode 3522 can each function as one electrodeof a liquid crystal element, and by applying voltage therebetween,alignment of liquid crystals can be controlled.

For example, the electrode 3522 is electrically connected to theabove-described wiring 3510 or wiring 3511; thus, the pixel of theabove-described touch panel can be formed.

Note that the electrode 3522 can be provided over the electrode 3523. Inthat case, the electrode 3522 may have an opening and may be providedover the electrode 3523 with an insulating film provided therebetween.

FIG. 28B is a cross-sectional schematic diagram illustrating part of apixel having an IPS mode of a liquid crystal display device.

The electrode 3523 and electrode 3522 provided in the pixel each have acomb-like shape and are provided on the same plane.

For example, the electrode 3522 is electrically connected to theabove-described wiring 3510 or wiring 3511; thus, the pixel of theabove-described touch panel can be formed.

FIG. 28C is a cross-sectional schematic diagram illustrating part of apixel having a VA mode of a liquid crystal display device.

The electrode 3522 is provided so as to face the electrode 3523 with theliquid crystal 3524 provided therebetween. The wiring 3526 is providedon the electrode 3522. For example, the wiring 3526 can be provided toelectrically connect the block including the pixel illustrated in FIG.28C and blocks different from the block including the pixel illustratedin FIG. 28C.

For example, the electrode 3522 is electrically connected to theabove-described wiring 3510 or wiring 3511; thus, the pixel of theabove-described touch panel can be formed.

<3-3. Microcomputer>

The transistors described above can be applied to a microcomputer usedfor a variety of electronic appliances.

A structure and operation of a fire alarm that is an example of theelectronic appliance using a microcomputer are described with referenceto FIG. 29, FIG. 30, FIGS. 31A to 31C, and FIG. 32A.

The fire alarm in this specification refers to any system which raisesan alarm over fire occurrence instantly and includes, for example, aresidential fire alarm, an automatic fire alarm system, and a firedetector used for the automatic fire alarm system in its category.

An alarm system illustrated in FIG. 29 includes at least a microcomputer500. The microcomputer 500 is provided inside the alarm system. Themicrocomputer 500 includes a power gate controller 503 electricallyconnected to a high potential power supply line VDD, a power gate 504electrically connected to the high potential power supply line VDD andthe power gate controller 503, a central processing unit (CPU) 505electrically connected to the power gate 504, and a sensor portion 509electrically connected to the power gate 504 and the CPU 505. Further,the CPU 505 includes a volatile memory portion 506 and a nonvolatilememory portion 507.

The CPU 505 is electrically connected to a bus line 502 via an interface508. The interface 508 as well as the CPU 505 is electrically connectedto the power gate 504. As a bus standard of the interface 508, forexample, an I²C bus can be used. A light-emitting element 530electrically connected to the power gate 504 via the interface 508 isprovided in the alarm system.

The light-emitting element 530 is preferably an element which emitslight with high directivity, and for example, an organic EL element, aninorganic EL element, or an LED can be used.

The power gate controller 503 includes a timer and controls the powergate 504 with the use of the timer. The power gate 504 allows or stopssupply of power from the high potential power supply line VDD to the CPU505, the sensor portion 509, and the interface 508, in accordance withthe control by the power gate controller 503. Here, as an example of thepower gate 504, a switching element such as a transistor can be given.

With the use of the power gate controller 503 and the power gate 504,power is supplied to the sensor portion 509, the CPU 505, and theinterface 508 in a period during which the amount of light is measured,and supply of power to the sensor portion 509, the CPU 505, and theinterface 508 can be stopped during an interval between measurementperiods. The alarm system operates in such a manner, whereby powerconsumption can be reduced as compared to the case where power iscontinuously supplied to the above structures.

In the case where a transistor is used as the power gate 504, it ispreferable to use a transistor which has extremely low off-state currentand is used for the nonvolatile memory portion 507, for example, any ofthe transistors each of which includes the multilayer film including theoxide semiconductor layer. With the use of such a transistor, leakagecurrent can be reduced when supply of power is stopped by the power gate504, so that power consumption can be reduced.

A direct-current power source 501 may be provided in the alarm system sothat power is supplied from the direct-current power source 501 to thehigh potential power supply line VDD. An electrode of the direct-currentpower source 501 on the high potential side is electrically connected tothe high potential power supply line VDD, and an electrode of thedirect-current power source 501 on the low potential side iselectrically connected to a low potential power supply line VSS. The lowpotential power supply line VSS is electrically connected to themicrocomputer 500. Here, the high potential power supply line VDD issupplied with a high potential H. The low potential power supply lineVSS is supplied with a low potential L, for example, a ground potential(GND).

In the case where a battery is used as the direct-current power source501, for example, a battery case which includes an electrodeelectrically connected to the high potential power supply line VDD, anelectrode electrically connected to the low potential power supply lineVSS, and a housing which can hold the battery is provided in a housing.Note that the alarm system does not necessarily include thedirect-current power source 501 and may have, for example, a structurein which power is supplied from an alternate-current power sourceprovided outside the alarm system through a wiring.

As the above battery, a secondary battery such as a lithium ionsecondary battery (also called a lithium ion storage battery or alithium ion battery) can be used. Further, a solar battery is preferablyprovided to charge the secondary battery.

The sensor portion 509 measures a physical quantity relating to anabnormal situation and transmits a measured value to the CPU 505. Aphysical quantity relating to an abnormal situation depends on the usageof the alarm system, and in an alarm system functioning as a fire alarm,a physical quantity relating to a fire is measured. Thus, the sensorportion 509 measures the amount of light as a physical quantity relatingto a fire and senses smoke.

The sensor portion 509 includes an optical sensor 511 electricallyconnected to the power gate 504, an amplifier 512 electrically connectedto the power gate 504, and an AD converter 513 electrically connected tothe power gate 504 and the CPU 505. The light-emitting element 530, theoptical sensor 511, the amplifier 512, and the AD converter 513 operatewhen the power gate 504 allows supply of power to the sensor portion509.

FIG. 30 illustrates part of the cross section of the alarm system. Ann-channel transistor 519 includes element isolation regions 403 in ap-type semiconductor substrate 401, a gate insulating film 407, a gateelectrode 409, n-type impurity regions 411 a and 411 b, an insulatingfilm 415, and an insulating film 417. The n-channel transistor 519 isformed using a semiconductor such as single crystal silicon, so that then-channel transistor 519 can operate at high speed. Accordingly, avolatile memory portion of a CPU that can achieve high-speed access canbe formed.

In addition, contact plugs 419 a and 419 b are formed in openings whichare formed by partly etching the insulating films 415 and 417, and aninsulating film 421 having groove portions is formed over the insulatingfilm 417 and the contact plugs 419 a and 419 b. Wirings 423 a and 423 bare formed in the groove portions of the insulating film 421. Aninsulating film 420 is formed over the insulating film 421 and thewirings 423 a and 423 b by a sputtering method, a CVD method, or thelike, and an insulating film 422 having a groove portion is formed overthe insulating film 420. An electrode 424 is formed in the grooveportion of the insulating film 422. The electrode 424 functions as aback gate electrode of a second transistor 517. The electrode 424 cancontrol the threshold voltage of the second transistor 517.

Moreover, an insulating film 425 is formed over the insulating film 422and the electrode 424 by a sputtering method, a CVD method, or the like.

The second transistor 517 and a photoelectric conversion element 514 areprovided over the insulating film 425. The second transistor 517includes the multilayer film 406 including the oxide semiconductor layer406 a and the oxide semiconductor layer 406 b, the source electrode 416a and the drain electrode 416 b which are over and in contact with themultilayer film 406, the gate insulating film 412, the gate electrode404, and the protective insulating film 418. Moreover, an insulatingfilm 445 which covers the photoelectric conversion element 514 and thesecond transistor 517 is formed, and a wiring 449 in contact with thedrain electrode 416 b is formed over the insulating film 445. The wiring449 functions as a node which electrically connects the drain electrode416 b of the second transistor 517 to the gate electrode 409 of then-channel transistor 519.

The optical sensor 511 includes the photoelectric conversion element514, a capacitor, a first transistor, the second transistor 517, a thirdtransistor, and the n-channel transistor 519. As the photoelectricconversion element 514, a photodiode can be used here, for example.

One of terminals of the photoelectric conversion element 514 iselectrically connected to the low potential power supply line VSS, andthe other of the terminals thereof is electrically connected to one ofthe source electrode and the drain electrode of the second transistor517. The gate electrode of the second transistor 517 is supplied with anelectric charge accumulation control signal Tx, and the other of thesource electrode and the drain electrode thereof is electricallyconnected to one of a pair of electrodes of the capacitor, one of asource electrode and a drain electrode of the first transistor, and thegate electrode of the n-channel transistor 519 (hereinafter the node isreferred to as a node FD in some cases). The other of the pair ofelectrodes of the capacitor is electrically connected to the lowpotential power supply line VSS. A gate electrode of the firsttransistor is supplied with a reset signal Res, and the other of thesource electrode and the drain electrode thereof is electricallyconnected to the high potential power supply line VDD. One of a sourceelectrode and a drain electrode of the n-channel transistor 519 iselectrically connected to one of a source electrode and a drainelectrode of the third transistor and the amplifier 512. The other ofthe source electrode and the drain electrode of the n-channel transistor519 is electrically connected to the high potential power supply lineVDD. A gate electrode of the third transistor is supplied with a biassignal Bias, and the other of the source electrode and the drainelectrode thereof is electrically connected to the low potential powersupply line VSS.

Note that the capacitor is not necessarily provided. For example, in thecase where parasitic capacitance of the n-channel transistor 519 or thelike is sufficiently large, a structure without the capacitor may beemployed.

Further, as each of the first transistor and the second transistor 517,the transistor with extremely low off-state current is preferably used.As the transistor with extremely low off-state current, any of the abovetransistors each of which includes the multilayer film including theoxide semiconductor layer is preferably used. With such a structure, thepotential of the node FD can be held for a long time.

In the structure in FIG. 30, the photoelectric conversion element 514 iselectrically connected to the second transistor 517 and is provided overthe insulating film 425.

The photoelectric conversion element 514 includes a semiconductor film460 over the insulating film 425, and the source electrode 416 a and anelectrode 416 c which are in contact with the top surface of thesemiconductor film 460. The source electrode 416 a is an electrodefunctioning as the source electrode or the drain electrode of the secondtransistor 517 and electrically connects the photoelectric conversionelement 514 to the second transistor 517.

Over the semiconductor film 460, the source electrode 416 a, and theelectrode 416 c, the gate insulating film 412, the protective insulatingfilm 418, and the insulating film 445 are provided. Further, a wiring456 is formed over the insulating film 445 and is in contact with theelectrode 416 c through an opening provided in the gate insulating film412, the protective insulating film 418, and the insulating film 445.

The electrode 416 c can be formed in steps similar to those of thesource electrode 416 a and the drain electrode 416 b, and the wiring 456can be formed in steps similar to those of the wiring 449.

As the semiconductor film 460, a semiconductor film which can performphotoelectric conversion is provided, and for example, silicon,germanium, or the like can be used. In the case of using silicon for thesemiconductor film 460, an optical sensor which senses visible light canbe obtained. Further, there is a difference between silicon andgermanium in wavelengths of absorbed electromagnetic waves. In the caseof using germanium for the semiconductor film 460, a sensor which sensesinfrared rays can be obtained.

In the above manner, the sensor portion 509 including the optical sensor511 can be incorporated into the microcomputer 500, so that the numberof components can be reduced and the housing of the alarm system can bereduced in size.

In the fire alarm including the above-described IC chip, the CPU 505 inwhich a plurality of circuits each including any of the abovetransistors are combined and mounted on one IC chip is used.

<3-3-1. Cpu>

FIGS. 31A to 31C are block diagrams illustrating a specific structure ofa CPU at least partly including any of the above transistors.

The CPU illustrated in FIG. 31A includes an arithmetic logic unit (ALU)1191, an ALU controller 1192, an instruction decoder 1193, an interruptcontroller 1194, a timing controller 1195, a register 1196, a registercontroller 1197, a bus interface (Bus I/F) 1198, a rewritable ROM 1199,and a ROM interface (ROM I/F) 1189 over a substrate 1190. Asemiconductor substrate, an SOI substrate, a glass substrate, or thelike is used as the substrate 1190. The ROM 1199 and the ROM interface1189 may be provided over separate chips. Needless to say, the CPU inFIG. 31A is just an example of a simplified structure, and an actual CPUmay have a variety of structures depending on the application.

An instruction that is input to the CPU through the bus interface 1198is input to the instruction decoder 1193 and decoded therein, and then,input to the ALU controller 1192, the interrupt controller 1194, theregister controller 1197, and the timing controller 1195.

The ALU controller 1192, the interrupt controller 1194, the registercontroller 1197, and the timing controller 1195 conduct various controlsin accordance with the decoded instruction. Specifically, the ALUcontroller 1192 generates signals for controlling the operation of theALU 1191. While the CPU is executing a program, the interrupt controller1194 judges an interrupt request from an external input/output device ora peripheral circuit on the basis of its priority or a mask state, andprocesses the request. The register controller 1197 generates an addressof the register 1196, and reads/writes data from/to the register 1196 inaccordance with the state of the CPU.

The timing controller 1195 generates signals for controlling operationtimings of the ALU 1191, the ALU controller 1192, the instructiondecoder 1193, the interrupt controller 1194, and the register controller1197. For example, the timing controller 1195 includes an internal clockgenerator for generating an internal clock signal CLK2 based on areference clock signal CLK1, and supplies the internal clock signal CLK2to the above circuits.

In the CPU illustrated in FIG. 31A, a memory cell is provided in theregister 1196. For the memory cell of the register 1196, the abovetransistor can be used.

In the CPU illustrated in FIG. 31A, the register controller 1197 selectsan operation of holding data in the register 1196 in accordance with aninstruction from the ALU 1191. That is, the register controller 1197selects whether data is held by a flip-flop or by a capacitor in thememory cell included in the register 1196. When data holding by theflip-flop is selected, a power supply voltage is supplied to the memorycell in the register 1196. When data holding by the capacitor isselected, the data is rewritten in the capacitor, and supply of powersupply voltage to the memory cell in the register 1196 can be stopped.

The power supply can be stopped by a switching element provided betweena memory cell group and a node to which a power supply potential VDD ora power supply potential VSS is supplied, as illustrated in FIG. 31B orFIG. 31C. Circuits illustrated in FIGS. 31B and 31C are described below.

FIGS. 31B and 31C each illustrate a memory device in which any of theabove transistors is used as a switching element which controls supplyof a power supply potential to a memory cell.

The memory device illustrated in FIG. 31B includes a switching element1141 and a memory cell group 1143 including a plurality of memory cells1142. Specifically, for each of the memory cells 1142, the abovetransistor can be used. Each of the memory cells 1142 included in thememory cell group 1143 is supplied with the high-level power supplypotential VDD via the switching element 1141. Further, each of thememory cells 1142 included in the memory cell group 1143 is suppliedwith a potential of a signal IN and the low-level power supply potentialVSS.

In FIG. 31B, any of the above transistors is used as the switchingelement 1141, and the switching of the transistor is controlled by asignal SigA supplied to a gate electrode layer thereof.

Note that FIG. 31B illustrates the structure in which the switchingelement 1141 includes only one transistor; however, one embodiment ofthe present invention is not limited thereto and the switching element1141 may include a plurality of transistors. In the case where theswitching element 1141 includes a plurality of transistors which serveas switching elements, the plurality of transistors may be connected toeach other in parallel, in series, or in combination of parallelconnection and series connection.

Although the switching element 1141 controls the supply of thehigh-level power supply potential VDD to each of the memory cells 1142included in the memory cell group 1143 in FIG. 31B, the switchingelement 1141 may control the supply of the low-level power supplypotential VSS.

FIG. 31C illustrates an example of a memory device in which each of thememory cells 1142 included in the memory cell group 1143 is suppliedwith the low-level power supply potential VSS via the switching element1141. The supply of the low-level power supply potential VSS to each ofthe memory cells 1142 included in the memory cell group 1143 can becontrolled by the switching element 1141.

When a switching element is provided between a memory cell group and anode to which the power supply potential VDD or the power supplypotential VSS is supplied, data can be held even in the case where anoperation of a CPU is temporarily stopped and the supply of the powersupply voltage is stopped; accordingly, power consumption can bereduced. Specifically, for example, while a user of a personal computerdoes not input data to an input device such as a keyboard, the operationof the CPU can be stopped, so that the power consumption can be reduced.

Although the CPU is given as an example, the transistor can also beapplied to an LSI such as a digital signal processor (DSP), a customLSI, or a field programmable gate array (FPGA).

<3-3-2. Installation Example>

In a television set 8000 in FIG. 32A, a display portion 8002 isincorporated in a housing 8001. The display portion 8002 can display animage and a speaker portion 8003 can output sound. The above transistorcan be used for the display portion 8002.

A semiconductor display device such as a liquid crystal display device,a light-emitting device in which a light-emitting element such as anorganic EL element is provided in each pixel, an electrophoresis displaydevice, a digital micromirror device (DMD), or a plasma display panel(PDP) can be used for the display portion 8002.

In addition, the television set 8000 may include a CPU for performinginformation communication or a memory. A CPU or a memory that uses anyof the above transistors, the above memory device, or the above CPUconsumes less power.

In FIG. 32A, an alarm system 8100 is a residential fire alarm, whichincludes a sensor portion and a microcomputer 8101. The microcomputer8101 includes a CPU in which any of the above transistors is used.

In FIG. 32A, a CPU that uses any of the above transistors is included inan air conditioner which includes an indoor unit 8200 and an outdoorunit 8204. Specifically, the indoor unit 8200 includes a housing 8201,an air outlet 8202, a CPU 8203, and the like. Although the CPU 8203 isprovided in the indoor unit 8200 in FIG. 32A, the CPU 8203 may beprovided in the outdoor unit 8204. Alternatively, the CPU 8203 may beprovided in both the indoor unit 8200 and the outdoor unit 8204. A CPUthat uses any of the above transistors can save the power of the airconditioner.

In FIG. 32A, a CPU that uses any of the above transistors is included inan electric refrigerator-freezer 8300. Specifically, the electricrefrigerator-freezer 8300 includes a housing 8301, a door for arefrigerator 8302, a door for a freezer 8303, a CPU 8304, and the like.In FIG. 32A, the CPU 8304 is provided in the housing 8301. A CPU thatuses any of the above transistors can save the power of the electricrefrigerator-freezer 8300.

FIGS. 32B and 32C illustrate an example of an electric vehicle. Anelectric vehicle 9700 is equipped with a secondary battery 9701. Theoutput of the electric power of the secondary battery 9701 is adjustedby a control circuit 9702 and the electric power is supplied to adriving device 9703. The control circuit 9702 is controlled by aprocessing unit 9704 including a ROM, a RAM, a CPU, or the like which isnot illustrated. A CPU that uses any of the above transistors can savethe power of the electric vehicle 9700.

The driving device 9703 includes a DC motor or an AC motor either aloneor in combination with an internal-combustion engine. The processingunit 9704 outputs a control signal to the control circuit 9702 on thebasis of input data such as data of operation (e.g., acceleration,deceleration, or stop) by a driver or data during driving (e.g., data onan upgrade or a downgrade, or data on a load on a driving wheel) of theelectric vehicle 9700. The control circuit 9702 adjusts the electricenergy supplied from the secondary battery 9701 in accordance with thecontrol signal of the processing unit 9704 to control the output of thedriving device 9703. In the case where the AC motor is mounted, althoughnot illustrated, an inverter which converts direct current intoalternate current is also incorporated.

This embodiment shows an example of a basic principle. Thus, part of orthe whole of this embodiment can be freely combined with, applied to, orreplaced with part of or the whole of another embodiment.

Example 1

In this example, photoresponse of an oxide semiconductor layer wasevaluated. In addition, electrical characteristics of a transistorincluding the oxide semiconductor layer in a channel formation regionwere evaluated.

Sample 1 has the structure illustrated in FIGS. 1A and 1B. Note that aglass substrate was used as the substrate 100. As the insulating film112, a stack of a 50-nm-thick silicon oxynitride layer and a400-nm-thick silicon nitride layer over the silicon oxynitride layer wasused. For the electrode 116 a and the electrode 116 b, a stack of a50-nm-thick tungsten layer, a 400-nm-thick aluminum layer over thetungsten layer, and a 100-nm-thick titanium layer over the aluminumlayer was used. As the insulating film 118, a 450-nm-thick siliconoxynitride film containing excess oxygen was used.

As the oxide semiconductor layer 106 a 1, a 35-nm-thick oxidesemiconductor layer formed by a sputtering method using a targetcontaining In, Ga, and Zn at an atomic ratio of 1:1:1 was used. As theoxide semiconductor layer 106 a 2, a 20-nm-thick oxide semiconductorlayer formed by a sputtering method using a target containing In, Ga,and Zn at an atomic ratio of 1:3:2 was used.

Sample 2 has the structure illustrated in FIGS. 3A and 3B. Note that aglass substrate was used as the substrate 100. As the insulating film112, a stack of a 50-nm-thick silicon oxynitride layer and a400-nm-thick silicon nitride layer over the silicon oxynitride layer wasused. For the electrode 116 a and the electrode 116 b, a stack of a50-nm-thick tungsten layer, a 400-nm-thick aluminum layer over thetungsten layer, and a 100-nm-thick titanium layer over the aluminumlayer was used. As the insulating film 118, a 450-nm-thick siliconoxynitride film containing excess oxygen was used.

As the oxide semiconductor layer 106 b, a 35-nm-thick oxidesemiconductor layer formed by a sputtering method using a targetcontaining In, Ga, and Zn at an atomic ratio of 1:1:1 was used.

Sample 3 has the structure illustrated in FIGS. 5A and 5B. Note that aglass substrate was used as the substrate 100. As the insulating film112, a stack of a 50-nm-thick silicon oxynitride layer and a400-nm-thick silicon nitride layer over the silicon oxynitride layer wasused. For the electrode 116 a and the electrode 116 b, a stack of a50-nm-thick tungsten layer, a 400-nm-thick aluminum layer over thetungsten layer, and a 100-nm-thick titanium layer over the aluminumlayer was used. As the insulating film 118, a 450-nm-thick siliconoxynitride film containing excess oxygen was used.

As the oxide semiconductor layer 106 c 1, a 20-nm-thick oxidesemiconductor layer formed by a sputtering method using a targetcontaining In, Ga, and Zn at an atomic ratio of 1:3:2 was used. As theoxide semiconductor layer 106 c 2, a 35-nm-thick oxide semiconductorlayer formed by a sputtering method using a target containing In, Ga,and Zn at an atomic ratio of 1:1:1 was used.

FIGS. 33A and 33B show the structure of Sample 4. FIG. 33B is across-sectional view of Sample 4 taken along dashed-dotted line A4-B4 inFIG. 33A.

FIG. 33B is a cross-sectional view of Sample 4 including the substrate100; the insulating film 112 provided over the substrate 100; amultilayer film 106 d including an oxide semiconductor layer 106 d 1over the insulating film 112, an oxide semiconductor layer 106 d 2 overthe oxide semiconductor layer 106 d 1, and an oxide semiconductor layer106 d 3 over the oxide semiconductor layer 106 d 2; the electrode 116 aand the electrode 116 b provided over and in contact with the multilayerfilm 106 d; and the insulating film 118 provided over the multilayerfilm 106 d, the electrode 116 a, and the electrode 116 b.

Note that a glass substrate was used as the substrate 100. As theinsulating film 112, a stack of a 50-nm-thick silicon oxynitride layerand a 400-nm-thick silicon nitride layer over the silicon oxynitridelayer was used. For the electrode 116 a and the electrode 116 b, a stackof a 50-nm-thick tungsten layer, a 400-nm-thick aluminum layer over thetungsten layer, and a 100-nm-thick titanium layer over the aluminumlayer was used. As the insulating film 118, a 450-nm-thick siliconoxynitride film containing excess oxygen was used.

As the oxide semiconductor layer 106 d 1, a 20-nm-thick oxidesemiconductor layer formed by a sputtering method using a targetcontaining In, Ga, and Zn at an atomic ratio of 1:3:2 was used. As theoxide semiconductor layer 106 d 2, a 35-nm-thick oxide semiconductorlayer formed by a sputtering method using a target containing In, Ga,and Zn at an atomic ratio of 1:1:1 was used. As the oxide semiconductorlayer 106 d 3, a 20-nm-thick oxide semiconductor layer formed by asputtering method using a target containing In, Ga, and Zn at an atomicratio of 1:3:2 was used.

Note that the same deposition conditions were employed in the sputteringfor forming the oxide semiconductor layer 106 a 1, the oxidesemiconductor layer 106 b, the oxide semiconductor layer 106 c 2, andthe oxide semiconductor layer 106 d 2. Further, the same depositionconditions were employed in the sputtering for forming the oxidesemiconductor layer 106 a 2, the oxide semiconductor layer 106 c 1, theoxide semiconductor layer 106 d 1, and the oxide semiconductor layer 106d 3.

Further, the substrate 100, the insulating film 112, the electrode 116a, the electrode 116 b, and the insulating film 118 in Samples 1 to 4were each formed under the same conditions.

Samples 1 to 4 were subjected to first heat treatment before theformation of the insulating film 118. The first heat treatment wasperformed at 450° C. in a nitrogen gas atmosphere for one hour, and thenat 450° C. in an atmosphere containing 80% nitrogen gas and 20% oxygengas for one hour. Further, Samples 1 to 4 were subjected to second heattreatment after the formation of the insulating film 118. The secondheat treatment was performed at 350° C. in an atmosphere containing 80%nitrogen gas and 20% oxygen gas for one hour.

Next, photoresponse of Samples 1 to 4 was evaluated. Note that inSamples 1 to 4, the distance between the electrode 116 a and theelectrode 116 b (denoted by “distance between electrodes” in FIG. 33A)was 5 μm, and the length of opposite sides of the electrode 116 a andthe electrode 116 b (denoted by “length of opposite sides” in FIG. 33A)was 1000 μm. Irradiation light was light of a xenon lamp (centerwavelength: 350 nm) that has passed through a band-pass filter. Theintensity of the light was 3.0 mW/cm². The irradiation light had aspectrum denoted by “light 1” (solid line) in FIG. 34. The measurementtemperature was room temperature (20° C. to 25° C.).

Photoresponse was evaluated as follows. While a voltage of 0.1 V wasapplied between the electrode 116 a and the electrode 116 b, three stepswere performed: the samples were put in a dark state for 60 seconds(first step), then irradiated with light for 180 seconds (second step),and then put in a dark state for 240 seconds (third step). Further,current value was measured. FIGS. 35A to 35D show the measurementresults. Photoresponse of Sample 1, photoresponse of Sample 2,photoresponse of Sample 3, and photoresponse of Sample 4 are shown inFIG. 35A, FIG. 35B, FIG. 35C, and FIG. 35D, respectively. Measurementrange was adjusted for each sample in order to accurately measure thecurrent value during light irradiation. Therefore, in some samples,current value in the first step and/or the third step performed in adark state is smaller than the lower limit of measurement. Note thatwhen the current value is close to or smaller than the lower limit ofmeasurement, the measured current value might include a large amount ofnoise.

According to Models A to C described in the embodiment, the oxidesemiconductor layer 106 a 1 with a low density of trap states serves asa main current path in Sample 1, and the oxide semiconductor layer 106 d2 with a low density of trap states serves as a main current path inSample 4. Meanwhile, the oxide semiconductor layer 106 b with a highdensity of trap states serves as a main current path in Sample 2, andthe oxide semiconductor layer 106 c 2 with a high density of trap statesserves as a main current path in Sample 3. Therefore, a larger amount ofcurrent flows upon light irradiation in Samples 1 and 4 than in Samples2 and 3. Note that the maximum current values in Sample 1, Sample 2,Sample 3, and Sample 4 were 1.8×10⁻⁶ A, 1.3×10⁻⁸ A, 3.0×10⁻⁷ A, and3.0×10⁻⁶ A, respectively.

Further, according to Models A to C described in the embodiment, inSamples 1 and 4, the step in which recombination of electrons and holesproceeds rapidly occupies a relatively small proportion of the periodduring which the recombination proceeds, and the step in which therecombination proceeds slowly occupies a relatively large proportion ofthe period. On the other hand, in Sample 2, the step in whichrecombination of electrons and holes proceeds rapidly occupies arelatively large proportion of the period during which the recombinationproceeds, and the step in which the recombination proceeds slowlyoccupies a relatively small proportion of the period. Further, in Sample3, the step in which recombination of electrons and holes proceedsrapidly occupies most of the period during which the recombinationproceeds, and the step in which the recombination proceeds slowlyoccupies a small proportion of the period. Therefore, in Samples 1 and4, as compared with Sample 2, a relatively large amount of current flowsfor a long time even after light irradiation is stopped. In Sample 3,current hardly flows after light irradiation is stopped.

FIGS. 36A to 36D show the results of photoresponse with normalizedcurrent values obtained by dividing the current values in FIGS. 35A to35D by the maximum current values. Photoresponse of Sample 1,photoresponse of Sample 2, photoresponse of Sample 3, and photoresponseof Sample 4 are shown in FIG. 36A, FIG. 36B, FIG. 36C, and FIG. 36D,respectively.

According to FIG. 36A, the normalized current value (currentvalue/maximum current value) of Sample 1 at a time five seconds afterthe start of light irradiation was 0.89, and that at a time five secondsafter the stop of light irradiation was 0.42. According to FIG. 36B, thenormalized current value of Sample 2 at a time five seconds after thestart of light irradiation was 0.68, and that at a time five secondsafter the stop of light irradiation was 0.04. According to FIG. 36C, thenormalized current value of Sample 3 at a time five seconds after thestart of light irradiation was 0.97, and that at a time five secondsafter the stop of light irradiation was 0.00. According to FIG. 36D, thenormalized current value of Sample 4 at a time five seconds after thestart of light irradiation was 0.88, and that at a time five secondsafter the stop of light irradiation was 0.32.

Next, Transistors 1 to 4 corresponding to Samples 1 to 4 werefabricated. FIGS. 37A to 37D illustrate the structures of Transistors 1to 4.

FIG. 37A illustrates the structure of Transistor 1. A glass substratewas used as a substrate 900. A 100-nm-thick tungsten film was used as agate electrode 904. As a gate insulating film 912, a stack of a50-nm-thick silicon oxynitride layer and a 400-nm-thick silicon nitridelayer over the silicon oxynitride layer was used. For a source electrode916 a and a drain electrode 916 b, a stack of a 50-nm-thick tungstenlayer, a 400-nm-thick aluminum layer over the tungsten layer, and a100-nm-thick titanium layer over the aluminum layer was used. As aprotective insulating film 918, a 450-nm-thick silicon oxynitride filmcontaining excess oxygen was used.

In Transistor 1, as an oxide semiconductor layer 906 a 1, a 35-nm-thickoxide semiconductor layer formed by a sputtering method using a targetcontaining In, Ga, and Zn at an atomic ratio of 1:1:1 was used. As anoxide semiconductor layer 906 a 2, a 20-nm-thick oxide semiconductorlayer formed by a sputtering method using a target containing In, Ga,and Zn at an atomic ratio of 1:3:2 was used.

FIG. 37B illustrates the structure of Transistor 2. A glass substratewas used as the substrate 900. A 100-nm-thick tungsten film was used asthe gate electrode 904. As the gate insulating film 912, a stack of a50-nm-thick silicon oxynitride layer and a 400-nm-thick silicon nitridelayer over the silicon oxynitride layer was used. For the sourceelectrode 916 a and the drain electrode 916 b, a stack of a 50-nm-thicktungsten layer, a 400-nm-thick aluminum layer over the tungsten layer,and a 100-nm-thick titanium layer over the aluminum layer was used. Asthe protective insulating film 918, a 450-nm-thick silicon oxynitridefilm containing excess oxygen was used.

In Transistor 2, as an oxide semiconductor layer 906 b, a 35-nm-thickoxide semiconductor layer formed by a sputtering method using a targetcontaining In, Ga, and Zn at an atomic ratio of 1:1:1 was used.

FIG. 37C illustrates the structure of Transistor 3. A glass substratewas used as the substrate 900. A 100-nm-thick tungsten film was used asthe gate electrode 904. As the gate insulating film 912, a stack of a50-nm-thick silicon oxynitride layer and a 400-nm-thick silicon nitridelayer over the silicon oxynitride layer was used. For the sourceelectrode 916 a and the drain electrode 916 b, a stack of a 50-nm-thicktungsten layer, a 400-nm-thick aluminum layer over the tungsten layer,and a 100-nm-thick titanium layer over the aluminum layer was used. Asthe protective insulating film 918, a 450-nm-thick silicon oxynitridefilm containing excess oxygen was used.

In Transistor 3, as an oxide semiconductor layer 906 c 1, a 20-nm-thickoxide semiconductor layer formed by a sputtering method using a targetcontaining In, Ga, and Zn at an atomic ratio of 1:3:2 was used. As anoxide semiconductor layer 906 c 2, a 35-nm-thick oxide semiconductorlayer formed by a sputtering method using a target containing In, Ga,and Zn at an atomic ratio of 1:1:1 was used.

FIG. 37D illustrates the structure of Transistor 4. A glass substratewas used as the substrate 900. A 100-nm-thick tungsten film was used asthe gate electrode 904. As the gate insulating film 912, a stack of a50-nm-thick silicon oxynitride layer and a 400-nm-thick silicon nitridelayer over the silicon oxynitride layer was used. For the sourceelectrode 916 a and the drain electrode 916 b, a stack of a 50-nm-thicktungsten layer, a 400-nm-thick aluminum layer over the tungsten layer,and a 100-nm-thick titanium layer over the aluminum layer was used. Asthe protective insulating film 918, a 450-nm-thick silicon oxynitridefilm containing excess oxygen was used.

In Transistor 4, as an oxide semiconductor layer 906 d 1, a 20-nm-thickoxide semiconductor layer formed by a sputtering method using a targetcontaining In, Ga, and Zn at an atomic ratio of 1:3:2 was used. As anoxide semiconductor layer 906 d 2, a 35-nm-thick oxide semiconductorlayer formed by a sputtering method using a target containing In, Ga,and Zn at an atomic ratio of 1:1:1 was used. As an oxide semiconductorlayer 906 d 3, a 20-nm-thick oxide semiconductor layer formed by asputtering method using a target containing In, Ga, and Zn at an atomicratio of 1:3:2 was used.

Note that the same deposition conditions were employed in the sputteringfor forming the oxide semiconductor layer 906 a 1, the oxidesemiconductor layer 906 b, the oxide semiconductor layer 906 c 2, andthe oxide semiconductor layer 906 d 2. Further, the same depositionconditions were employed in the sputtering for forming the oxidesemiconductor layer 906 a 2, the oxide semiconductor layer 906 c 1, theoxide semiconductor layer 906 d 1, and the oxide semiconductor layer 906d 3.

Further, the substrate 900, the gate electrode 904, the gate insulatingfilm 912, the source electrode 916 a, the drain electrode 916 b, and theprotective insulating film 918 in Transistors 1 to 4 were each formedunder the same conditions.

Transistors 1 to 4 were subjected to first heat treatment before theformation of the protective insulating film 918. The first heattreatment was performed at 450° C. in a nitrogen gas atmosphere for onehour, and then at 450° C. in an atmosphere containing 80% nitrogen gasand 20% oxygen gas for one hour. Further, Transistors 1 to 4 weresubjected to second heat treatment after the formation of the protectiveinsulating film 918. The second heat treatment was performed at 350° C.in an atmosphere containing 80% nitrogen gas and 20% oxygen gas for onehour.

In the above manner, Transistors 1 to 4 corresponding to Samples 1 to 4were prepared.

Next, gate BT stress tests (GBT tests) were performed on the Transistors1 to 4. The GBT tests were performed in a dark state (dark) or a lightstate (photo). Note that in the light state, the transistors wereirradiated with white LED light with 3000 lx. FIG. 38 shows an emissionspectrum of the white LED light used in the GBT test in the light state.

The GBT tests were performed on the transistors with a channel length Lof 6 μm and a channel width W of 50 μm. The Vg-Id characteristics weremeasured by measurement of drain current under the conditions that thedrain voltage was 10 V and the gate voltage was swept from −30 V to 30V.

In the positive GBT test (+GBT), first, the substrate temperature wasset to 80° C. and first measurement of Vg-Id characteristics wasconducted. After that, the transistors were held for 2000 seconds at agate voltage Vg of 30 V and a drain voltage Vd of 0 V, and then secondmeasurement of Vg-Id characteristics was conducted.

In the negative GBT test (−GBT), first, the substrate temperature wasset to 80° C. and first measurement of Vg-Id characteristics wasconducted. After that, the transistors were held for 2000 seconds at agate voltage Vg of −30 V and a drain voltage Vd of 0 V, and then secondmeasurement of Vg-Id characteristics was conducted.

FIGS. 39A and 39B show changes in threshold voltage (ΔVth) and shiftvalue (ΔShift) between before and after the GBT tests.

Note that the threshold voltage (Vth) refers to a gate voltage when achannel is formed (voltage between a source and a gate). In a curvewhere the horizontal axis indicates the gate voltage (Vg) and thevertical axis indicates the square root of drain current (Id; currentbetween a source and a drain) and where data are plotted (Vg−√Idcharacteristics), the threshold voltage was defined as a gate voltage ata point of intersection of an extrapolated tangent line having thehighest inclination with the square root of drain current of 0 (Id=0 A).In a curve where the horizontal axis indicates the gate voltage (Vg) andthe vertical axis indicates the logarithm of the drain current (Id) andwhere data are plotted, the shift value (Shift) is defined as a gatevoltage at a point of intersection of an extrapolated tangent linehaving the highest inclination with a drain current of 1×10⁻¹² A.

According to FIGS. 39A and 39B, the amounts of change in thresholdvoltage and shift value of Transistor 1 were smaller than those ofTransistor 2, particularly by the positive GBT test in a dark state.Further, the amounts of change in threshold voltage and shift value ofTransistor 1 were smaller than those of Transistor 3, particularly bythe positive GBT test in a dark state and by the positive GBT test in alight state.

This is presumably because Transistor 1 has a lower density of trapstates in the channel formation region than those of Transistors 2 and3, and thus fluctuations of electrical characteristics due to capture ofcharges by the trap states are small.

According to FIGS. 39A and 39B, the amounts of change in thresholdvoltage and shift value of Transistor 4 were smaller than those ofTransistor 3, particularly by the positive GBT test in a dark state.

This is presumably because, like Transistor 1, Transistor 4 has a lowerdensity of trap states in the channel formation region than that ofTransistor 3, and thus fluctuations of electrical characteristics due tocapture of charges by the trap states are small.

This example shows that the density of trap states in the main currentpath in the oxide semiconductor layer can be evaluated by photoresponse.This example also shows that a transistor with a low density of trapstates in the channel formation region (main current path) has stableelectrical characteristics.

This example can be implemented in appropriate combination with theembodiment or Example 2.

Example 2

In this example, photoresponse of Samples 1 and 2 described in Example 1was evaluated under conditions different from those in Example 1.

FIGS. 40A and 40B show the photoresponse to irradiation light withintensities of 0.3 mW/cm², 1 mW/cm², and 3 mW/cm². FIG. 40A shows thephotoresponse of Sample 1, and FIG. 40B shows the photoresponse ofSample 2. Refer to Example 1 for description on other conditions forevaluating photoresponse.

According to FIGS. 40A and 40B, current value is increased as theintensity of light with which Samples 1 and 2 are irradiated isincreased.

FIGS. 41A and 41B show the results of photoresponse in FIGS. 40A and 40Bthat are converted into normalized current values. FIG. 41A shows thephotoresponse of Sample 1, and FIG. 41B shows the photoresponse ofSample 2.

According to FIGS. 41A and 41B, even in the case where the intensity ofirradiation light is varied, the results of photoresponse are similarwhen converted into normalized current values.

FIGS. 42A and 42B show the photoresponse to irradiation light with acenter wavelength of 350 nm (see “light1” in FIG. 34), light with acenter wavelength of 450 nm (see “light2” in FIG. 34), and light with acenter wavelength of 550 nm (see “light3” in FIG. 34). FIG. 42A showsthe photoresponse of Sample 1, and FIG. 42B shows the photoresponse ofSample 2. Refer to Example 1 for description on other conditions forevaluating photoresponse.

According to FIGS. 42A and 42B, the current value is increased as thecenter wavelength of light with which Samples 1 and 2 are irradiated isshortened.

FIGS. 43A and 43B show the results of photoresponse in FIGS. 42A and 42Bthat are converted into normalized current values. FIG. 43A shows thephotoresponse of Sample 1, and FIG. 43B shows the photoresponse ofSample 2.

According to FIGS. 43A and 43B, in the case where the center wavelengthof irradiation light is varied, the results of photoresponse are notsimilar even when converted into normalized current values. Accordingly,in evaluating trap states by photoresponse, it is preferable to uselight with a center wavelength suitable for a sample to be measured.

FIGS. 44A and 44B show the photoresponse at measurement temperatures of−30° C., 40° C., and 125° C. FIG. 44A shows the photoresponse of Sample1, and FIG. 44B shows the photoresponse of Sample 2. Refer to Example 1for description on other conditions for evaluating photoresponse.

According to FIGS. 44A and 44B, as the measurement temperature ofSamples 1 and 2 is increased, the value of current that flows uponirradiation of the samples is decreased. Further, in Sample 1, thehigher the measurement temperature is, the sooner the current value isdecreased after the stop of light irradiation. In Sample 2, the currentvalue is decreased sooner after the stop of light irradiation at themeasurement temperature of −30° C. than at 40° C. and 125° C.

FIGS. 45A and 45B show the results of photoresponse in FIGS. 44A and 44Bthat are converted into normalized current values. FIG. 45A shows thephotoresponse of Sample 1, and FIG. 45B shows the photoresponse ofSample 2.

The results of photoresponse in FIGS. 45A and 45B where current valuesare converted into normalized current values show tendencies similar tothose in FIGS. 44A and 44B.

According to Model A described in the embodiment, the step in whichrecombination of electrons and holes proceeds slowly follows the stop oflight irradiation in Sample 1. The results show that, on the assumptionthat movement of electrons from the conduction band of the oxidesemiconductor layer 906 a 1 to the conduction band of the oxidesemiconductor layer 906 a 2 limits the speed of the step, recombinationproceeds more rapidly as the measurement temperature is increased.

According to Model B described in the embodiment, the step in whichrecombination of electrons and holes proceeds rapidly follows the stopof light irradiation in Sample 2. The results show that, on theassumption that state-to-state recombination in the oxide semiconductorlayer 906 b causes the step, electrons or holes captured by the trapstates are excited again more easily as the measurement temperature isincreased.

FIGS. 44A and 44B and FIGS. 45A and 45B show that more information canbe obtained from photoresponse by changing measurement temperature.Accordingly, in evaluating trap states by photoresponse, it ispreferable to vary the measurement temperature.

This example can be implemented in appropriate combination with theembodiment or Example 1.

Note that in this specification and the like, in a diagram or a textdescribed in one embodiment or example, part of the diagram or the textis taken out, and one embodiment of the invention can be constituted.Thus, in the case where a diagram or a text related to a certain part isdescribed, a content taken out from the diagram or the text of thecertain part is also disclosed as one embodiment of the invention andcan constitute one embodiment of the invention. Therefore, for example,part of a diagram or a text including one or more of active elements(e.g., transistors and diodes), wirings, passive elements (e.g.,capacitors and resistors), conductive layers, insulating layers,semiconductor layers, organic materials, inorganic materials,components, devices, operating methods, manufacturing methods, and thelike can be taken out to constitute one embodiment of the invention. Forexample, M circuit elements (e.g., transistors or capacitors) (M is aninteger) are picked up from a circuit diagram in which N circuitelements (e.g., transistors or capacitors) (N is an integer, where M<N)are provided, whereby one embodiment of the invention can beconstituted. As another example, M layers (M is an integer) are pickedup from a cross-sectional view in which N layers (N is an integer, whereM<N) are provided, whereby one embodiment of the invention can beconstituted. As another example, M elements (M is an integer) are pickedup from a flow chart in which N elements (N is an integer, where M<N)are provided, whereby one embodiment of the invention can beconstituted.

Note that, in the case where at least one specific example isillustrated in a diagram or a text described in one embodiment in thisspecification and the like, it will be readily appreciated by thoseskilled in the art that a broader concept of the specific example can bederived. Therefore, in the case where at least one specific example isillustrated in the diagram or the text described in one embodiment, abroader concept of the specific example is disclosed as one embodimentof the invention and can constitute one embodiment of the invention.

Note that, in this specification and the like, a content illustrated inat least a diagram (which may be part of the diagram) is disclosed asone embodiment of the invention and can constitute one embodiment of theinvention. Therefore, when a certain content is illustrated in adiagram, the content is disclosed as one embodiment of the inventioneven without text description and can constitute one embodiment of theinvention. Similarly, a diagram obtained by taking out part of a diagramis disclosed as one embodiment of the invention and can constitute oneembodiment of the invention.

This application is based on Japanese Patent Application serial no.2012-263819 filed with Japan Patent Office on Nov. 30, 2012, the entirecontents of which are hereby incorporated by reference.

1-10. (canceled)
 11. A semiconductor device comprising: a transistorincluding an oxide semiconductor layer in a channel formation region,the oxide semiconductor layer being electrically connected to a firstelectrode and a second electrode, wherein, while a voltage is appliedbetween the first electrode and the second electrode, the oxidesemiconductor layer begins to be irradiated with light having a peakintensity in a wavelength range of 340 nm to 360 nm and an intensity of3 mW/cm² at a temperature of 25° C. at a time T0 and irradiation isstopped at a time T1, wherein a value of a current flowing between thefirst electrode and the second electrode at a time T2 is greater than orequal to 70% and less than 100% of a maximum value of a current flowingbetween the first electrode and the second electrode between the time T0and the time T1, wherein a value of a current flowing between the firstelectrode and the second electrode at a time T3 is greater than or equalto 5% and less than 100% of the maximum value of the current flowingbetween the first electrode and the second electrode between the time T0and the time T1, wherein the time T2 is after a period of greater thanor equal to 1 second and less than or equal to 15 seconds from the timeT0 and before the time T1, and wherein the time T3 is after a period ofgreater than or equal to 1 second and less than or equal to 15 secondsfrom the time T1.
 12. The semiconductor device according to claim 11,wherein the time T2 is five seconds after the time T0, and wherein thetime T3 is five seconds after the time T1.
 13. The semiconductor deviceaccording to claim 11, wherein the time T1 is after a period of greaterthan or equal to 100 seconds and less than or equal to 300 seconds fromthe time T0.
 14. The semiconductor device according to claim 11, whereinthe oxide semiconductor layer includes a first oxide semiconductor layerand a second oxide semiconductor layer over the first oxidesemiconductor layer, and wherein the second oxide semiconductor layerhas a lower electron affinity than an electron affinity of the firstoxide semiconductor layer.
 15. The semiconductor device according toclaim 11, further comprising an insulating film in contact with theoxide semiconductor layer and a third electrode overlapping with theoxide semiconductor layer with the insulating film interposedtherebetween.
 16. The semiconductor device according to claim 11,wherein the oxide semiconductor layer comprises at least indium. 17.(canceled)